188 		WREG32(mmBIF_FB_EN, 0);  in gmc_v8_0_mc_stop()
192 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);  in gmc_v8_0_mc_stop()
205 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v8_0_mc_resume()
209 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v8_0_mc_resume()
250 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);  in gmc_v8_0_init_microcode()
323 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_tonga_mc_load_microcode()
324 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_tonga_mc_load_microcode()
328 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_tonga_mc_load_microcode()
329 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_tonga_mc_load_microcode()
333 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_tonga_mc_load_microcode()
336 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_tonga_mc_load_microcode()
337 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_tonga_mc_load_microcode()
338 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_tonga_mc_load_microcode()
390 	WREG32(mmMC_SEQ_MISC0, data);  in gmc_v8_0_polaris_mc_load_microcode()
394 		WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_polaris_mc_load_microcode()
395 		WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_polaris_mc_load_microcode()
398 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_polaris_mc_load_microcode()
399 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_polaris_mc_load_microcode()
403 		WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_polaris_mc_load_microcode()
406 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_polaris_mc_load_microcode()
407 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_polaris_mc_load_microcode()
408 	WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_polaris_mc_load_microcode()
449 		WREG32((0xb05 + j), 0x00000000);  in gmc_v8_0_mc_program()
450 		WREG32((0xb06 + j), 0x00000000);  in gmc_v8_0_mc_program()
451 		WREG32((0xb07 + j), 0x00000000);  in gmc_v8_0_mc_program()
452 		WREG32((0xb08 + j), 0x00000000);  in gmc_v8_0_mc_program()
453 		WREG32((0xb09 + j), 0x00000000);  in gmc_v8_0_mc_program()
455 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v8_0_mc_program()
464 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v8_0_mc_program()
469 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v8_0_mc_program()
472 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v8_0_mc_program()
474 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v8_0_mc_program()
476 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v8_0_mc_program()
482 		WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v8_0_mc_program()
484 		WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));  in gmc_v8_0_mc_program()
485 		WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));  in gmc_v8_0_mc_program()
486 		WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in gmc_v8_0_mc_program()
489 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v8_0_mc_program()
490 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
491 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
496 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);  in gmc_v8_0_mc_program()
500 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v8_0_mc_program()
503 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v8_0_mc_program()
640 			WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb_pasid()
671 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_flush_gpu_tlb()
759 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_set_fault_enable_default()
792 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v8_0_set_prt()
799 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);  in gmc_v8_0_set_prt()
800 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);  in gmc_v8_0_set_prt()
801 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);  in gmc_v8_0_set_prt()
802 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);  in gmc_v8_0_set_prt()
803 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
804 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
805 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
806 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);  in gmc_v8_0_set_prt()
808 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
809 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
810 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
811 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);  in gmc_v8_0_set_prt()
812 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
813 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
814 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
815 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);  in gmc_v8_0_set_prt()
853 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_enable()
863 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_enable()
867 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v8_0_gart_enable()
874 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v8_0_gart_enable()
889 	WREG32(mmVM_L2_CNTL4, tmp);  in gmc_v8_0_gart_enable()
891 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);  in gmc_v8_0_gart_enable()
892 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);  in gmc_v8_0_gart_enable()
893 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);  in gmc_v8_0_gart_enable()
894 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
896 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v8_0_gart_enable()
901 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_gart_enable()
903 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);  in gmc_v8_0_gart_enable()
904 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);  in gmc_v8_0_gart_enable()
905 	WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);  in gmc_v8_0_gart_enable()
912 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v8_0_gart_enable()
913 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v8_0_gart_enable()
916 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v8_0_gart_enable()
919 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v8_0_gart_enable()
924 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
926 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v8_0_gart_enable()
939 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_gart_enable()
982 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v8_0_gart_disable()
983 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v8_0_gart_disable()
989 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_disable()
993 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_disable()
994 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v8_0_gart_disable()
1364 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1370 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1410 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1414 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1420 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1424 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1509 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1513 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1517 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1521 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_medium_grain_clock_gating()
1525 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1529 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1533 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1537 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1541 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1545 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1549 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1553 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1557 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_medium_grain_clock_gating()
1561 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1565 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1569 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1573 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1577 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_medium_grain_clock_gating()
1589 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_light_sleep()
1593 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_light_sleep()
1597 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1601 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_light_sleep()
1605 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_light_sleep()
1609 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_light_sleep()
1613 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_light_sleep()
1617 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1621 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_light_sleep()
1625 		WREG32(mmMC_HUB_MISC_HUB_CG, data);  in fiji_update_mc_light_sleep()
1629 		WREG32(mmMC_HUB_MISC_SIP_CG, data);  in fiji_update_mc_light_sleep()
1633 		WREG32(mmMC_HUB_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1637 		WREG32(mmMC_XPB_CLK_GAT, data);  in fiji_update_mc_light_sleep()
1641 		WREG32(mmATC_MISC_CG, data);  in fiji_update_mc_light_sleep()
1645 		WREG32(mmMC_CITF_MISC_WR_CG, data);  in fiji_update_mc_light_sleep()
1649 		WREG32(mmMC_CITF_MISC_RD_CG, data);  in fiji_update_mc_light_sleep()
1653 		WREG32(mmMC_CITF_MISC_VM_CG, data);  in fiji_update_mc_light_sleep()
1657 		WREG32(mmVM_L2_CG, data);  in fiji_update_mc_light_sleep()