188 	uint32_t tmp;  in gfxhub_v2_0_init_tlb_regs()  local
191 	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v2_0_init_tlb_regs()
193 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v2_0_init_tlb_regs()
194 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v2_0_init_tlb_regs()
195 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
197 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
199 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v2_0_init_tlb_regs()
200 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
203 	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v2_0_init_tlb_regs()
208 	uint32_t tmp;  in gfxhub_v2_0_init_cache_regs()  local
215 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);  in gfxhub_v2_0_init_cache_regs()
216 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v2_0_init_cache_regs()
217 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);  in gfxhub_v2_0_init_cache_regs()
218 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v2_0_init_cache_regs()
221 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v2_0_init_cache_regs()
223 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v2_0_init_cache_regs()
224 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v2_0_init_cache_regs()
225 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v2_0_init_cache_regs()
226 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);  in gfxhub_v2_0_init_cache_regs()
228 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);  in gfxhub_v2_0_init_cache_regs()
229 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v2_0_init_cache_regs()
230 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v2_0_init_cache_regs()
231 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);  in gfxhub_v2_0_init_cache_regs()
233 	tmp = mmGCVM_L2_CNTL3_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
235 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v2_0_init_cache_regs()
236 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v2_0_init_cache_regs()
239 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v2_0_init_cache_regs()
240 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v2_0_init_cache_regs()
243 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);  in gfxhub_v2_0_init_cache_regs()
245 	tmp = mmGCVM_L2_CNTL4_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
246 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v2_0_init_cache_regs()
247 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v2_0_init_cache_regs()
248 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);  in gfxhub_v2_0_init_cache_regs()
250 	tmp = mmGCVM_L2_CNTL5_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
251 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);  in gfxhub_v2_0_init_cache_regs()
252 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);  in gfxhub_v2_0_init_cache_regs()
257 	uint32_t tmp;  in gfxhub_v2_0_enable_system_domain()  local
259 	tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);  in gfxhub_v2_0_enable_system_domain()
260 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v2_0_enable_system_domain()
261 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v2_0_enable_system_domain()
262 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,  in gfxhub_v2_0_enable_system_domain()
264 	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);  in gfxhub_v2_0_enable_system_domain()
288 	uint32_t tmp;  in gfxhub_v2_0_setup_vmid_config()  local
291 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);  in gfxhub_v2_0_setup_vmid_config()
292 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v2_0_setup_vmid_config()
293 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v2_0_setup_vmid_config()
295 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
297 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
299 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
301 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
303 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
305 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
307 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
309 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
313 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
317 				    i * hub->ctx_distance, tmp);  in gfxhub_v2_0_setup_vmid_config()
363 	u32 tmp;  in gfxhub_v2_0_gart_disable()  local
372 	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v2_0_gart_disable()
373 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v2_0_gart_disable()
374 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_gart_disable()
376 	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v2_0_gart_disable()
394 	u32 tmp;  in gfxhub_v2_0_set_fault_enable_default()  local
395 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v2_0_set_fault_enable_default()
396 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
398 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
400 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
402 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
404 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
407 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
409 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
411 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
413 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
415 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
417 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
420 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
422 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
425 	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v2_0_set_fault_enable_default()