502 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_update_vs_emph()  argument
505 	amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,  in amdgpu_atombios_dp_update_vs_emph()
507 					       0, dp_info->train_set[0]); /* sets all lanes at once */  in amdgpu_atombios_dp_update_vs_emph()
510 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,  in amdgpu_atombios_dp_update_vs_emph()
511 			  dp_info->train_set, dp_info->dp_lane_count);  in amdgpu_atombios_dp_update_vs_emph()
515 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)  in amdgpu_atombios_dp_set_tp()  argument
531 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);  in amdgpu_atombios_dp_set_tp()
534 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);  in amdgpu_atombios_dp_set_tp()
538 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_init()  argument
540 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);  in amdgpu_atombios_dp_link_train_init()
545 	amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);  in amdgpu_atombios_dp_link_train_init()
548 	if (dp_info->dpcd[3] & 0x1)  in amdgpu_atombios_dp_link_train_init()
549 		drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
552 		drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
556 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);  in amdgpu_atombios_dp_link_train_init()
559 	tmp = dp_info->dp_lane_count;  in amdgpu_atombios_dp_link_train_init()
560 	if (drm_dp_enhanced_frame_cap(dp_info->dpcd))  in amdgpu_atombios_dp_link_train_init()
562 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);  in amdgpu_atombios_dp_link_train_init()
565 	tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);  in amdgpu_atombios_dp_link_train_init()
566 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);  in amdgpu_atombios_dp_link_train_init()
569 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,  in amdgpu_atombios_dp_link_train_init()
573 	drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_init()
581 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_finish()  argument
586 	drm_dp_dpcd_writeb(dp_info->aux,  in amdgpu_atombios_dp_link_train_finish()
591 	amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,  in amdgpu_atombios_dp_link_train_finish()
598 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_cr()  argument
604 	amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);  in amdgpu_atombios_dp_link_train_cr()
605 	memset(dp_info->train_set, 0, 4);  in amdgpu_atombios_dp_link_train_cr()
606 	amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_cr()
612 	dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_cr()
615 		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);  in amdgpu_atombios_dp_link_train_cr()
617 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in amdgpu_atombios_dp_link_train_cr()
618 						 dp_info->link_status) <= 0) {  in amdgpu_atombios_dp_link_train_cr()
623 		if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in amdgpu_atombios_dp_link_train_cr()
628 		for (i = 0; i < dp_info->dp_lane_count; i++) {  in amdgpu_atombios_dp_link_train_cr()
629 			if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)  in amdgpu_atombios_dp_link_train_cr()
632 		if (i == dp_info->dp_lane_count) {  in amdgpu_atombios_dp_link_train_cr()
637 		if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {  in amdgpu_atombios_dp_link_train_cr()
638 			++dp_info->tries;  in amdgpu_atombios_dp_link_train_cr()
639 			if (dp_info->tries == 5) {  in amdgpu_atombios_dp_link_train_cr()
644 			dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_cr()
646 		voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;  in amdgpu_atombios_dp_link_train_cr()
649 		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,  in amdgpu_atombios_dp_link_train_cr()
650 					     dp_info->train_set);  in amdgpu_atombios_dp_link_train_cr()
652 		amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_cr()
659 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in amdgpu_atombios_dp_link_train_cr()
660 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>  in amdgpu_atombios_dp_link_train_cr()
667 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)  in amdgpu_atombios_dp_link_train_ce()  argument
671 	if (dp_info->tp3_supported)  in amdgpu_atombios_dp_link_train_ce()
672 		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);  in amdgpu_atombios_dp_link_train_ce()
674 		amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);  in amdgpu_atombios_dp_link_train_ce()
677 	dp_info->tries = 0;  in amdgpu_atombios_dp_link_train_ce()
680 		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);  in amdgpu_atombios_dp_link_train_ce()
682 		if (drm_dp_dpcd_read_link_status(dp_info->aux,  in amdgpu_atombios_dp_link_train_ce()
683 						 dp_info->link_status) <= 0) {  in amdgpu_atombios_dp_link_train_ce()
688 		if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {  in amdgpu_atombios_dp_link_train_ce()
694 		if (dp_info->tries > 5) {  in amdgpu_atombios_dp_link_train_ce()
700 		amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,  in amdgpu_atombios_dp_link_train_ce()
701 					     dp_info->train_set);  in amdgpu_atombios_dp_link_train_ce()
703 		amdgpu_atombios_dp_update_vs_emph(dp_info);  in amdgpu_atombios_dp_link_train_ce()
704 		dp_info->tries++;  in amdgpu_atombios_dp_link_train_ce()
712 			  dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,  in amdgpu_atombios_dp_link_train_ce()
713 			  (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)  in amdgpu_atombios_dp_link_train_ce()
727 	struct amdgpu_atombios_dp_link_train_info dp_info;  in amdgpu_atombios_dp_link_train()  local
745 			dp_info.tp3_supported = true;  in amdgpu_atombios_dp_link_train()
747 			dp_info.tp3_supported = false;  in amdgpu_atombios_dp_link_train()
749 		dp_info.tp3_supported = false;  in amdgpu_atombios_dp_link_train()
752 	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);  in amdgpu_atombios_dp_link_train()
753 	dp_info.adev = adev;  in amdgpu_atombios_dp_link_train()
754 	dp_info.encoder = encoder;  in amdgpu_atombios_dp_link_train()
755 	dp_info.connector = connector;  in amdgpu_atombios_dp_link_train()
756 	dp_info.dp_lane_count = dig_connector->dp_lane_count;  in amdgpu_atombios_dp_link_train()
757 	dp_info.dp_clock = dig_connector->dp_clock;  in amdgpu_atombios_dp_link_train()
758 	dp_info.aux = &amdgpu_connector->ddc_bus->aux;  in amdgpu_atombios_dp_link_train()
760 	if (amdgpu_atombios_dp_link_train_init(&dp_info))  in amdgpu_atombios_dp_link_train()
762 	if (amdgpu_atombios_dp_link_train_cr(&dp_info))  in amdgpu_atombios_dp_link_train()
764 	if (amdgpu_atombios_dp_link_train_ce(&dp_info))  in amdgpu_atombios_dp_link_train()
767 	if (amdgpu_atombios_dp_link_train_finish(&dp_info))  in amdgpu_atombios_dp_link_train()