40 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)  in amdgpu_virt_mmio_blocked()  argument
48 void amdgpu_virt_init_setting(struct amdgpu_device *adev)  in amdgpu_virt_init_setting()  argument
50 	struct drm_device *ddev = adev_to_drm(adev);  in amdgpu_virt_init_setting()
53 	if (adev->asic_type != CHIP_ALDEBARAN &&  in amdgpu_virt_init_setting()
54 	    adev->asic_type != CHIP_ARCTURUS) {  in amdgpu_virt_init_setting()
55 		if (adev->mode_info.num_crtc == 0)  in amdgpu_virt_init_setting()
56 			adev->mode_info.num_crtc = 1;  in amdgpu_virt_init_setting()
57 		adev->enable_virtual_display = true;  in amdgpu_virt_init_setting()
60 	adev->cg_flags = 0;  in amdgpu_virt_init_setting()
61 	adev->pg_flags = 0;  in amdgpu_virt_init_setting()
64 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,  in amdgpu_virt_kiq_reg_write_reg_wait()  argument
68 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;  in amdgpu_virt_kiq_reg_write_reg_wait()
107 	dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1);  in amdgpu_virt_kiq_reg_write_reg_wait()
117 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)  in amdgpu_virt_request_full_gpu()  argument
119 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_request_full_gpu()
123 		r = virt->ops->req_full_gpu(adev, init);  in amdgpu_virt_request_full_gpu()
127 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_request_full_gpu()
140 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)  in amdgpu_virt_release_full_gpu()  argument
142 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_release_full_gpu()
146 		r = virt->ops->rel_full_gpu(adev, init);  in amdgpu_virt_release_full_gpu()
150 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_release_full_gpu()
161 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)  in amdgpu_virt_reset_gpu()  argument
163 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_reset_gpu()
167 		r = virt->ops->reset_gpu(adev);  in amdgpu_virt_reset_gpu()
171 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_reset_gpu()
177 void amdgpu_virt_request_init_data(struct amdgpu_device *adev)  in amdgpu_virt_request_init_data()  argument
179 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_request_init_data()
182 		virt->ops->req_init_data(adev);  in amdgpu_virt_request_init_data()
184 	if (adev->virt.req_init_data_ver > 0)  in amdgpu_virt_request_init_data()
196 int amdgpu_virt_wait_reset(struct amdgpu_device *adev)  in amdgpu_virt_wait_reset()  argument
198 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_wait_reset()
203 	return virt->ops->wait_reset(adev);  in amdgpu_virt_wait_reset()
212 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)  in amdgpu_virt_alloc_mm_table()  argument
216 	if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)  in amdgpu_virt_alloc_mm_table()
219 	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,  in amdgpu_virt_alloc_mm_table()
221 				    &adev->virt.mm_table.bo,  in amdgpu_virt_alloc_mm_table()
222 				    &adev->virt.mm_table.gpu_addr,  in amdgpu_virt_alloc_mm_table()
223 				    (void *)&adev->virt.mm_table.cpu_addr);  in amdgpu_virt_alloc_mm_table()
229 	memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);  in amdgpu_virt_alloc_mm_table()
231 		 adev->virt.mm_table.gpu_addr,  in amdgpu_virt_alloc_mm_table()
232 		 adev->virt.mm_table.cpu_addr);  in amdgpu_virt_alloc_mm_table()
241 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)  in amdgpu_virt_free_mm_table()  argument
243 	if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)  in amdgpu_virt_free_mm_table()
246 	amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,  in amdgpu_virt_free_mm_table()
247 			      &adev->virt.mm_table.gpu_addr,  in amdgpu_virt_free_mm_table()
248 			      (void *)&adev->virt.mm_table.cpu_addr);  in amdgpu_virt_free_mm_table()
249 	adev->virt.mm_table.gpu_addr = 0;  in amdgpu_virt_free_mm_table()
273 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev)  in amdgpu_virt_init_ras_err_handler_data()  argument
275 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_init_ras_err_handler_data()
308 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev)  in amdgpu_virt_ras_release_bp()  argument
310 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_release_bp()
326 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev)  in amdgpu_virt_release_ras_err_handler_data()  argument
328 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_release_ras_err_handler_data()
336 	amdgpu_virt_ras_release_bp(adev);  in amdgpu_virt_release_ras_err_handler_data()
344 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev,  in amdgpu_virt_ras_add_bps()  argument
347 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_add_bps()
357 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev)  in amdgpu_virt_ras_reserve_bps()  argument
359 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_reserve_bps()
376 		if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT,  in amdgpu_virt_ras_reserve_bps()
388 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev,  in amdgpu_virt_ras_check_bad_page()  argument
391 	struct amdgpu_virt *virt = &adev->virt;  in amdgpu_virt_ras_check_bad_page()
405 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev,  in amdgpu_virt_add_bad_page()  argument
415 			retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va +  in amdgpu_virt_add_bad_page()
419 			if (amdgpu_virt_ras_check_bad_page(adev, retired_page))  in amdgpu_virt_add_bad_page()
422 			amdgpu_virt_ras_add_bps(adev, &bp, 1);  in amdgpu_virt_add_bad_page()
424 			amdgpu_virt_ras_reserve_bps(adev);  in amdgpu_virt_add_bad_page()
429 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev)  in amdgpu_virt_read_pf2vf_data()  argument
431 	struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf;  in amdgpu_virt_read_pf2vf_data()
438 	if (adev->virt.fw_reserve.p_pf2vf == NULL)  in amdgpu_virt_read_pf2vf_data()
450 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,  in amdgpu_virt_read_pf2vf_data()
451 			adev->virt.fw_reserve.checksum_key, checksum);  in amdgpu_virt_read_pf2vf_data()
457 		adev->virt.gim_feature =  in amdgpu_virt_read_pf2vf_data()
464 			adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size,  in amdgpu_virt_read_pf2vf_data()
471 		adev->virt.vf2pf_update_interval_ms =  in amdgpu_virt_read_pf2vf_data()
473 		adev->virt.gim_feature =  in amdgpu_virt_read_pf2vf_data()
475 		adev->virt.reg_access =  in amdgpu_virt_read_pf2vf_data()
478 		adev->virt.decode_max_dimension_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
479 		adev->virt.decode_max_frame_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
480 		adev->virt.encode_max_dimension_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
481 		adev->virt.encode_max_frame_pixels = 0;  in amdgpu_virt_read_pf2vf_data()
482 		adev->virt.is_mm_bw_enabled = false;  in amdgpu_virt_read_pf2vf_data()
485 			adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels);  in amdgpu_virt_read_pf2vf_data()
488 			adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels);  in amdgpu_virt_read_pf2vf_data()
491 			adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels);  in amdgpu_virt_read_pf2vf_data()
494 			adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels);  in amdgpu_virt_read_pf2vf_data()
496 		if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0))  in amdgpu_virt_read_pf2vf_data()
497 			adev->virt.is_mm_bw_enabled = true;  in amdgpu_virt_read_pf2vf_data()
499 		adev->unique_id =  in amdgpu_virt_read_pf2vf_data()
508 	if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000)  in amdgpu_virt_read_pf2vf_data()
509 		adev->virt.vf2pf_update_interval_ms = 2000;  in amdgpu_virt_read_pf2vf_data()
514 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev)  in amdgpu_virt_populate_vf2pf_ucode_info()  argument
517 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;  in amdgpu_virt_populate_vf2pf_ucode_info()
519 	if (adev->virt.fw_reserve.p_vf2pf == NULL)  in amdgpu_virt_populate_vf2pf_ucode_info()
522 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE,      adev->vce.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
523 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD,      adev->uvd.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
524 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC,       adev->gmc.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
525 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
526 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
527 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
528 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
529 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
530 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
531 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
532 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
533 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
534 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS,      adev->psp.sos.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
535 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD,      adev->psp.asd.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
536 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS,   adev->psp.ras.feature_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
537 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI,  adev->psp.xgmi.feature_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
538 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC,      adev->pm.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
539 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA,     adev->sdma.instance[0].fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
540 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2,    adev->sdma.instance[1].fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
541 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN,      adev->vcn.fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
542 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU,     adev->dm.dmcu_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
545 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)  in amdgpu_virt_write_vf2pf_data()  argument
548 	struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);  in amdgpu_virt_write_vf2pf_data()
550 	vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf;  in amdgpu_virt_write_vf2pf_data()
552 	if (adev->virt.fw_reserve.p_vf2pf == NULL)  in amdgpu_virt_write_vf2pf_data()
573 	vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;  in amdgpu_virt_write_vf2pf_data()
574 	vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;  in amdgpu_virt_write_vf2pf_data()
576 	amdgpu_virt_populate_vf2pf_ucode_info(adev);  in amdgpu_virt_write_vf2pf_data()
593 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work);  in amdgpu_virt_update_vf2pf_work_item()  local
596 	ret = amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_update_vf2pf_work_item()
599 	amdgpu_virt_write_vf2pf_data(adev);  in amdgpu_virt_update_vf2pf_work_item()
602 	schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);  in amdgpu_virt_update_vf2pf_work_item()
605 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev)  in amdgpu_virt_fini_data_exchange()  argument
607 	if (adev->virt.vf2pf_update_interval_ms != 0) {  in amdgpu_virt_fini_data_exchange()
609 		cancel_delayed_work_sync(&adev->virt.vf2pf_work);  in amdgpu_virt_fini_data_exchange()
610 		adev->virt.vf2pf_update_interval_ms = 0;  in amdgpu_virt_fini_data_exchange()
614 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)  in amdgpu_virt_init_data_exchange()  argument
620 	adev->virt.fw_reserve.p_pf2vf = NULL;  in amdgpu_virt_init_data_exchange()
621 	adev->virt.fw_reserve.p_vf2pf = NULL;  in amdgpu_virt_init_data_exchange()
622 	adev->virt.vf2pf_update_interval_ms = 0;  in amdgpu_virt_init_data_exchange()
624 	if (adev->mman.fw_vram_usage_va != NULL) {  in amdgpu_virt_init_data_exchange()
625 		adev->virt.vf2pf_update_interval_ms = 2000;  in amdgpu_virt_init_data_exchange()
627 		adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_init_data_exchange()
629 			(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_init_data_exchange()
630 		adev->virt.fw_reserve.p_vf2pf =  in amdgpu_virt_init_data_exchange()
632 			(adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10));  in amdgpu_virt_init_data_exchange()
634 		amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_init_data_exchange()
635 		amdgpu_virt_write_vf2pf_data(adev);  in amdgpu_virt_init_data_exchange()
638 		if (adev->virt.fw_reserve.p_pf2vf->version == 2) {  in amdgpu_virt_init_data_exchange()
639 				pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf;  in amdgpu_virt_init_data_exchange()
645 				if (bp_block_size && !adev->virt.ras_init_done)  in amdgpu_virt_init_data_exchange()
646 					amdgpu_virt_init_ras_err_handler_data(adev);  in amdgpu_virt_init_data_exchange()
648 				if (adev->virt.ras_init_done)  in amdgpu_virt_init_data_exchange()
649 					amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);  in amdgpu_virt_init_data_exchange()
651 	} else if (adev->bios != NULL) {  in amdgpu_virt_init_data_exchange()
652 		adev->virt.fw_reserve.p_pf2vf =  in amdgpu_virt_init_data_exchange()
654 			(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));  in amdgpu_virt_init_data_exchange()
656 		amdgpu_virt_read_pf2vf_data(adev);  in amdgpu_virt_init_data_exchange()
661 	if (adev->virt.vf2pf_update_interval_ms != 0) {  in amdgpu_virt_init_data_exchange()
662 		INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);  in amdgpu_virt_init_data_exchange()
663 		schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms);  in amdgpu_virt_init_data_exchange()
667 void amdgpu_detect_virtualization(struct amdgpu_device *adev)  in amdgpu_detect_virtualization()  argument
671 	switch (adev->asic_type) {  in amdgpu_detect_virtualization()
691 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;  in amdgpu_detect_virtualization()
694 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;  in amdgpu_detect_virtualization()
698 			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;  in amdgpu_detect_virtualization()
702 	if (amdgpu_sriov_vf(adev)) {  in amdgpu_detect_virtualization()
703 		switch (adev->asic_type) {  in amdgpu_detect_virtualization()
706 			vi_set_virt_ops(adev);  in amdgpu_detect_virtualization()
712 			soc15_set_virt_ops(adev);  in amdgpu_detect_virtualization()
717 			nv_set_virt_ops(adev);  in amdgpu_detect_virtualization()
719 			amdgpu_virt_request_init_data(adev);  in amdgpu_detect_virtualization()
722 			DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type);  in amdgpu_detect_virtualization()
728 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)  in amdgpu_virt_access_debugfs_is_mmio()  argument
730 	return amdgpu_sriov_is_debug(adev) ? true : false;  in amdgpu_virt_access_debugfs_is_mmio()
733 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)  in amdgpu_virt_access_debugfs_is_kiq()  argument
735 	return amdgpu_sriov_is_normal(adev) ? true : false;  in amdgpu_virt_access_debugfs_is_kiq()
738 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)  in amdgpu_virt_enable_access_debugfs()  argument
740 	if (!amdgpu_sriov_vf(adev) ||  in amdgpu_virt_enable_access_debugfs()
741 	    amdgpu_virt_access_debugfs_is_kiq(adev))  in amdgpu_virt_enable_access_debugfs()
744 	if (amdgpu_virt_access_debugfs_is_mmio(adev))  in amdgpu_virt_enable_access_debugfs()
745 		adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_enable_access_debugfs()
752 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev)  in amdgpu_virt_disable_access_debugfs()  argument
754 	if (amdgpu_sriov_vf(adev))  in amdgpu_virt_disable_access_debugfs()
755 		adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;  in amdgpu_virt_disable_access_debugfs()
758 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev)  in amdgpu_virt_get_sriov_vf_mode()  argument
762 	if (amdgpu_sriov_vf(adev)) {  in amdgpu_virt_get_sriov_vf_mode()
763 		if (amdgpu_sriov_is_pp_one_vf(adev))  in amdgpu_virt_get_sriov_vf_mode()
774 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,  in amdgpu_virt_update_sriov_video_codec()  argument
780 	if (!adev->virt.is_mm_bw_enabled)  in amdgpu_virt_update_sriov_video_codec()
785 			encode[i].max_width = adev->virt.encode_max_dimension_pixels;  in amdgpu_virt_update_sriov_video_codec()
786 			encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels;  in amdgpu_virt_update_sriov_video_codec()
796 			decode[i].max_width = adev->virt.decode_max_dimension_pixels;  in amdgpu_virt_update_sriov_video_codec()
797 			decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels;  in amdgpu_virt_update_sriov_video_codec()