Lines Matching +full:0 +full:x0000000b

36 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
39 #define VCN_DEC_KMD_CMD 		0x80000000
40 #define VCN_DEC_CMD_FENCE		0x00000000
41 #define VCN_DEC_CMD_TRAP		0x00000001
42 #define VCN_DEC_CMD_WRITE_REG		0x00000004
43 #define VCN_DEC_CMD_REG_READ_COND_WAIT	0x00000006
44 #define VCN_DEC_CMD_PACKET_START	0x0000000a
45 #define VCN_DEC_CMD_PACKET_END		0x0000000b
47 #define VCN_DEC_SW_CMD_NO_OP		0x00000000
48 #define VCN_DEC_SW_CMD_END		0x00000001
49 #define VCN_DEC_SW_CMD_IB		0x00000002
50 #define VCN_DEC_SW_CMD_FENCE		0x00000003
51 #define VCN_DEC_SW_CMD_TRAP		0x00000004
52 #define VCN_DEC_SW_CMD_IB_AUTO		0x00000005
53 #define VCN_DEC_SW_CMD_SEMAPHORE	0x00000006
54 #define VCN_DEC_SW_CMD_PREEMPT_FENCE	0x00000009
55 #define VCN_DEC_SW_CMD_REG_WRITE	0x0000000b
56 #define VCN_DEC_SW_CMD_REG_WAIT		0x0000000c
58 #define VCN_ENC_CMD_NO_OP		0x00000000
59 #define VCN_ENC_CMD_END 		0x00000001
60 #define VCN_ENC_CMD_IB			0x00000002
61 #define VCN_ENC_CMD_FENCE		0x00000003
62 #define VCN_ENC_CMD_TRAP		0x00000004
63 #define VCN_ENC_CMD_REG_WRITE		0x0000000b
64 #define VCN_ENC_CMD_REG_WAIT		0x0000000c
66 #define VCN_VID_SOC_ADDRESS_2_0 	0x1fa00
67 #define VCN1_VID_SOC_ADDRESS_3_0 	0x48200
68 #define VCN_AON_SOC_ADDRESS_2_0 	0x1f800
69 #define VCN1_AON_SOC_ADDRESS_3_0 	0x48000
70 #define VCN_VID_IP_ADDRESS_2_0		0x0
71 #define VCN_AON_IP_ADDRESS_2_0		0x30000
73 #define mmUVD_RBC_XX_IB_REG_CHECK 					0x026b
75 #define mmUVD_REG_XX_MASK 						0x026c
100 	} while (0)
109 		video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && 		\
110 				((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));	\
111 		video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) && 		\
112 				((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600)))));	\
113 		aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && 		\
114 				((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));	\
115 		aon1_range   = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) && 		\
116 				((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600)))));	\
118 			internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + 	\
121 			internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + 	\
124 			internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) + 	\
127 			internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) + 	\
130 			internal_reg_offset = (0xFFFFF & addr);					\
138 			(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |				\
149 				(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |			\
156 	} while (0)
162 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER	0x00000001
163 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER		0x00000001
171 	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
172 	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
173 	UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
174 	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
175 	UVD_STATUS__UVD_BUSY = 0x00000004,
176 	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
177 	UVD_STATUS__IDLE = 0x2,
178 	UVD_STATUS__BUSY = 0x5,
179 	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
180 	UVD_STATUS__RBC_BUSY = 0x1,
181 	UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
185 	VCN_DPG_STATE__UNPAUSE = 0,
283 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
284 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
285 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0