161 	r = request_firmware(&adev->vce.fw, fw_name, adev->dev);  in amdgpu_vce_sw_init()
168 	r = amdgpu_ucode_validate(adev->vce.fw);  in amdgpu_vce_sw_init()
172 		release_firmware(adev->vce.fw);  in amdgpu_vce_sw_init()
173 		adev->vce.fw = NULL;  in amdgpu_vce_sw_init()
177 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;  in amdgpu_vce_sw_init()
185 	adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) |  in amdgpu_vce_sw_init()
189 				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,  in amdgpu_vce_sw_init()
190 				    &adev->vce.gpu_addr, &adev->vce.cpu_addr);  in amdgpu_vce_sw_init()
197 		atomic_set(&adev->vce.handles[i], 0);  in amdgpu_vce_sw_init()
198 		adev->vce.filp[i] = NULL;  in amdgpu_vce_sw_init()
201 	INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);  in amdgpu_vce_sw_init()
202 	mutex_init(&adev->vce.idle_mutex);  in amdgpu_vce_sw_init()
218 	if (adev->vce.vcpu_bo == NULL)  in amdgpu_vce_sw_fini()
221 	drm_sched_entity_destroy(&adev->vce.entity);  in amdgpu_vce_sw_fini()
223 	amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,  in amdgpu_vce_sw_fini()
224 		(void **)&adev->vce.cpu_addr);  in amdgpu_vce_sw_fini()
226 	for (i = 0; i < adev->vce.num_rings; i++)  in amdgpu_vce_sw_fini()
227 		amdgpu_ring_fini(&adev->vce.ring[i]);  in amdgpu_vce_sw_fini()
229 	release_firmware(adev->vce.fw);  in amdgpu_vce_sw_fini()
230 	mutex_destroy(&adev->vce.idle_mutex);  in amdgpu_vce_sw_fini()
247 	ring = &adev->vce.ring[0];  in amdgpu_vce_entity_init()
249 	r = drm_sched_entity_init(&adev->vce.entity, DRM_SCHED_PRIORITY_NORMAL,  in amdgpu_vce_entity_init()
269 	cancel_delayed_work_sync(&adev->vce.idle_work);  in amdgpu_vce_suspend()
271 	if (adev->vce.vcpu_bo == NULL)  in amdgpu_vce_suspend()
275 		if (atomic_read(&adev->vce.handles[i]))  in amdgpu_vce_suspend()
298 	if (adev->vce.vcpu_bo == NULL)  in amdgpu_vce_resume()
301 	r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false);  in amdgpu_vce_resume()
307 	r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr);  in amdgpu_vce_resume()
309 		amdgpu_bo_unreserve(adev->vce.vcpu_bo);  in amdgpu_vce_resume()
314 	hdr = (const struct common_firmware_header *)adev->vce.fw->data;  in amdgpu_vce_resume()
318 		memcpy_toio(cpu_addr, adev->vce.fw->data + offset,  in amdgpu_vce_resume()
319 			    adev->vce.fw->size - offset);  in amdgpu_vce_resume()
323 	amdgpu_bo_kunmap(adev->vce.vcpu_bo);  in amdgpu_vce_resume()
325 	amdgpu_bo_unreserve(adev->vce.vcpu_bo);  in amdgpu_vce_resume()
340 		container_of(work, struct amdgpu_device, vce.idle_work.work);  in amdgpu_vce_idle_work_handler()
343 	for (i = 0; i < adev->vce.num_rings; i++)  in amdgpu_vce_idle_work_handler()
344 		count += amdgpu_fence_count_emitted(&adev->vce.ring[i]);  in amdgpu_vce_idle_work_handler()
357 		schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);  in amdgpu_vce_idle_work_handler()
376 	mutex_lock(&adev->vce.idle_mutex);  in amdgpu_vce_ring_begin_use()
377 	set_clocks = !cancel_delayed_work_sync(&adev->vce.idle_work);  in amdgpu_vce_ring_begin_use()
390 	mutex_unlock(&adev->vce.idle_mutex);  in amdgpu_vce_ring_begin_use()
403 		schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT);  in amdgpu_vce_ring_end_use()
416 	struct amdgpu_ring *ring = &adev->vce.ring[0];  in amdgpu_vce_free_handles()
419 		uint32_t handle = atomic_read(&adev->vce.handles[i]);  in amdgpu_vce_free_handles()
421 		if (!handle || adev->vce.filp[i] != filp)  in amdgpu_vce_free_handles()
428 		adev->vce.filp[i] = NULL;  in amdgpu_vce_free_handles()
429 		atomic_set(&adev->vce.handles[i], 0);  in amdgpu_vce_free_handles()
469 	if ((ring->adev->vce.fw_version >> 24) >= 52)  in amdgpu_vce_get_create_msg()
484 	if ((ring->adev->vce.fw_version >> 24) >= 52) {  in amdgpu_vce_get_create_msg()
565 		r = amdgpu_job_submit(job, &ring->adev->vce.entity,  in amdgpu_vce_get_destroy_msg()
698 		if (atomic_read(&p->adev->vce.handles[i]) == handle) {  in amdgpu_vce_validate_handle()
699 			if (p->adev->vce.filp[i] != p->filp) {  in amdgpu_vce_validate_handle()
709 		if (!atomic_cmpxchg(&p->adev->vce.handles[i], 0, handle)) {  in amdgpu_vce_validate_handle()
710 			p->adev->vce.filp[i] = p->filp;  in amdgpu_vce_validate_handle()
711 			p->adev->vce.img_size[i] = 0;  in amdgpu_vce_validate_handle()
822 			size = &p->adev->vce.img_size[session_idx];  in amdgpu_vce_ring_parse_cs()
952 			atomic_set(&p->adev->vce.handles[i], 0);  in amdgpu_vce_ring_parse_cs()
1042 			atomic_set(&p->adev->vce.handles[i], 0);  in amdgpu_vce_ring_parse_cs_vm()
1141 	if (ring != &ring->adev->vce.ring[0])  in amdgpu_vce_ring_test_ib()