66  * add to control->i2c_address, and then tell I2C layer to read
97 				       struct amdgpu_ras_eeprom_control *control)  in __get_eeprom_i2c_addr_arct()  argument
101 	if (!control || !atom_ctx)  in __get_eeprom_i2c_addr_arct()
107 		control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;  in __get_eeprom_i2c_addr_arct()
109 		control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;  in __get_eeprom_i2c_addr_arct()
115 				  struct amdgpu_ras_eeprom_control *control)  in __get_eeprom_i2c_addr()  argument
119 	if (!control)  in __get_eeprom_i2c_addr()
132 		control->i2c_address = ((u32) i2c_addr) << 16;  in __get_eeprom_i2c_addr()
139 		control->i2c_address = EEPROM_I2C_MADDR_VEGA20;  in __get_eeprom_i2c_addr()
143 		return __get_eeprom_i2c_addr_arct(adev, control);  in __get_eeprom_i2c_addr()
146 		control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;  in __get_eeprom_i2c_addr()
150 		control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;  in __get_eeprom_i2c_addr()
186 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)  in __write_table_header()  argument
189 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __write_table_header()
193 	__encode_table_header_to_buf(&control->tbl_hdr, buf);  in __write_table_header()
198 				  control->i2c_address +  in __write_table_header()
199 				  control->ras_header_offset,  in __write_table_header()
216 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)  in __calc_hdr_byte_sum()  argument
223 	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);  in __calc_hdr_byte_sum()
224 	pp = (u8 *) &control->tbl_hdr;  in __calc_hdr_byte_sum()
233 	struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_correct_header_tag()  argument
236 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_correct_header_tag()
248 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
251 	res = __write_table_header(control);  in amdgpu_ras_eeprom_correct_header_tag()
252 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
259  * @control: pointer to control structure
264 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_reset_table()  argument
266 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_reset_table()
270 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
277 	csum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_reset_table()
280 	res = __write_table_header(control);  in amdgpu_ras_eeprom_reset_table()
282 	control->ras_num_recs = 0;  in amdgpu_ras_eeprom_reset_table()
283 	control->ras_fri = 0;  in amdgpu_ras_eeprom_reset_table()
285 	amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_reset_table()
287 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
293 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,  in __encode_table_record_to_buf()  argument
321 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,  in __decode_table_record_from_buf()  argument
374  * @control: pointer to control structure
379  * The caller must hold the table mutex in @control.
382 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_write()  argument
385 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_write()
393 				  control->i2c_address +  in __amdgpu_ras_eeprom_write()
394 				  RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_write()
414 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append_table()  argument
430 		__encode_table_record_to_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_append_table()
436 	 * Let N = control->ras_max_num_record_count, then we have,  in amdgpu_ras_eeprom_append_table()
459 	a = control->ras_fri + control->ras_num_recs;  in amdgpu_ras_eeprom_append_table()
461 	if (b < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
462 		res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
463 	} else if (a < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
466 		g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
467 		g1 = b % control->ras_max_record_count + 1;  in amdgpu_ras_eeprom_append_table()
468 		res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
471 		res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
476 		if (g1 > control->ras_fri)  in amdgpu_ras_eeprom_append_table()
477 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
479 		a %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
480 		b %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
484 			res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
487 			if (b >= control->ras_fri)  in amdgpu_ras_eeprom_append_table()
488 				control->ras_fri = (b + 1) % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
496 			g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
498 			res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
501 			res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
506 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
509 	control->ras_num_recs = 1 + (control->ras_max_record_count + b  in amdgpu_ras_eeprom_append_table()
510 				     - control->ras_fri)  in amdgpu_ras_eeprom_append_table()
511 		% control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
518 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_update_header()  argument
520 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_update_header()
529 	    control->ras_num_recs >= ras->bad_page_cnt_threshold) {  in amdgpu_ras_eeprom_update_header()
532 			control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_update_header()
533 		control->tbl_hdr.header = RAS_TABLE_HDR_BAD;  in amdgpu_ras_eeprom_update_header()
536 	control->tbl_hdr.version = RAS_TABLE_VER;  in amdgpu_ras_eeprom_update_header()
537 	control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri);  in amdgpu_ras_eeprom_update_header()
538 	control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
539 	control->tbl_hdr.checksum = 0;  in amdgpu_ras_eeprom_update_header()
541 	buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
542 	buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);  in amdgpu_ras_eeprom_update_header()
545 			  control->tbl_hdr.tbl_size);  in amdgpu_ras_eeprom_update_header()
552 				 control->i2c_address +  in amdgpu_ras_eeprom_update_header()
553 				 control->ras_record_offset,  in amdgpu_ras_eeprom_update_header()
573 	csum += __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_update_header()
576 	control->tbl_hdr.checksum = csum;  in amdgpu_ras_eeprom_update_header()
577 	res = __write_table_header(control);  in amdgpu_ras_eeprom_update_header()
585  * @control: pointer to control structure
591  * can be appended is between 1 and control->ras_max_record_count,
596 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append()  argument
600 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_append()
609 	} else if (num > control->ras_max_record_count) {  in amdgpu_ras_eeprom_append()
611 			  num, control->ras_max_record_count);  in amdgpu_ras_eeprom_append()
615 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
617 	res = amdgpu_ras_eeprom_append_table(control, record, num);  in amdgpu_ras_eeprom_append()
619 		res = amdgpu_ras_eeprom_update_header(control);  in amdgpu_ras_eeprom_append()
621 		amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_append()
623 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
629  * @control: pointer to control structure
634  * The caller must hold the table mutex in @control.
637 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_read()  argument
640 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_read()
648 				 control->i2c_address +  in __amdgpu_ras_eeprom_read()
649 				 RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_read()
670  * @control: pointer to control structure
679 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_read()  argument
683 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_read()
694 	} else if (num > control->ras_num_recs) {  in amdgpu_ras_eeprom_read()
696 			  num, control->ras_num_recs);  in amdgpu_ras_eeprom_read()
724 	g0 = control->ras_fri + num - 1;  in amdgpu_ras_eeprom_read()
725 	g1 = g0 % control->ras_max_record_count;  in amdgpu_ras_eeprom_read()
726 	if (g0 < control->ras_max_record_count) {  in amdgpu_ras_eeprom_read()
730 		g0 = control->ras_max_record_count - control->ras_fri;  in amdgpu_ras_eeprom_read()
734 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
735 	res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);  in amdgpu_ras_eeprom_read()
739 		res = __amdgpu_ras_eeprom_read(control,  in amdgpu_ras_eeprom_read()
752 		__decode_table_record_from_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_read()
755 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
771 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_size_read()  local
778 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_size_read()
782 			       RAS_TBL_SIZE_BYTES, control->ras_max_record_count);  in amdgpu_ras_debugfs_eeprom_size_read()
819 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_table_size()  argument
822 		strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;  in amdgpu_ras_debugfs_table_size()
825 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_set_ret_size()  argument
827 	struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,  in amdgpu_ras_debugfs_set_ret_size()
832 		d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_set_ret_size()
840 	struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;  in amdgpu_ras_debugfs_table_read()  local
845 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
867 			 control->tbl_hdr.header,  in amdgpu_ras_debugfs_table_read()
868 			 control->tbl_hdr.version,  in amdgpu_ras_debugfs_table_read()
869 			 control->tbl_hdr.first_rec_offset,  in amdgpu_ras_debugfs_table_read()
870 			 control->tbl_hdr.tbl_size,  in amdgpu_ras_debugfs_table_read()
871 			 control->tbl_hdr.checksum);  in amdgpu_ras_debugfs_table_read()
897 	data_len = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_table_read()
913 		for ( ; size > 0 && s < control->ras_num_recs; s++) {  in amdgpu_ras_debugfs_table_read()
914 			u32 ai = RAS_RI_TO_AI(control, s);  in amdgpu_ras_debugfs_table_read()
917 			res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);  in amdgpu_ras_debugfs_table_read()
920 			__decode_table_record_from_buf(control, &record, dare);  in amdgpu_ras_debugfs_table_read()
923 				 RAS_INDEX_TO_OFFSET(control, ai),  in amdgpu_ras_debugfs_table_read()
945 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
955 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_table_read()  local
962 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_table_read()
990  * @control: pointer to control structure
998 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)  in __verify_ras_table_checksum()  argument
1000 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __verify_ras_table_checksum()
1005 		control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in __verify_ras_table_checksum()
1013 				 control->i2c_address +  in __verify_ras_table_checksum()
1014 				 control->ras_header_offset,  in __verify_ras_table_checksum()
1033 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_init()  argument
1036 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_init()
1038 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_init()
1051 	if (!__get_eeprom_i2c_addr(adev, control))  in amdgpu_ras_eeprom_init()
1054 	control->ras_header_offset = RAS_HDR_START;  in amdgpu_ras_eeprom_init()
1055 	control->ras_record_offset = RAS_RECORD_START;  in amdgpu_ras_eeprom_init()
1056 	control->ras_max_record_count  = RAS_MAX_RECORD_COUNT;  in amdgpu_ras_eeprom_init()
1057 	mutex_init(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_init()
1061 				 control->i2c_address + control->ras_header_offset,  in amdgpu_ras_eeprom_init()
1070 	control->ras_num_recs = RAS_NUM_RECS(hdr);  in amdgpu_ras_eeprom_init()
1071 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);  in amdgpu_ras_eeprom_init()
1075 				 control->ras_num_recs);  in amdgpu_ras_eeprom_init()
1076 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_init()
1082 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_init()
1086 		if (ras->bad_page_cnt_threshold > control->ras_num_recs) {  in amdgpu_ras_eeprom_init()
1089 			 * ras->bad_page_cnt_threshold - control->num_recs > 0,  in amdgpu_ras_eeprom_init()
1096 				 control->ras_num_recs,  in amdgpu_ras_eeprom_init()
1098 			res = amdgpu_ras_eeprom_correct_header_tag(control,  in amdgpu_ras_eeprom_init()
1105 				control->ras_num_recs, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_init()
1110 		res = amdgpu_ras_eeprom_reset_table(control);  in amdgpu_ras_eeprom_init()