16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
68 	if (!amdgpu_pmu_attr->type)  in amdgpu_pmu_event_show()
69 		return sprintf(buf, "%s\n", amdgpu_pmu_attr->event_str);  in amdgpu_pmu_event_show()
72 			amdgpu_pmu_attr->event_str, amdgpu_pmu_attr->type);  in amdgpu_pmu_event_show()
79 	const char *name;  member
99  *  - PMU typed
105  *  - Event config typed
115 	{ .name = "event", .config = "config:0-7" },
116 	{ .name = "instance", .config = "config:8-15" },
117 	{ .name = "umask", .config = "config:16-23"},
118 	{ .name = "type", .config = "config:56-63"}
123 	{ .name = "xgmi_link0_data_outbound",
124 			.config = "event=0x7,instance=0x46,umask=0x2" },
125 	{ .name = "xgmi_link1_data_outbound",
126 			.config = "event=0x7,instance=0x47,umask=0x2" }
145 	{ .name = "event", .config = "config:0-7" },
146 	{ .name = "instance", .config = "config:8-15" },
147 	{ .name = "umask", .config = "config:16-23"}
151 	{ .name = "cake0_pcsout_txdata",
152 			.config = "event=0x7,instance=0x46,umask=0x2" },
153 	{ .name = "cake1_pcsout_txdata",
154 			.config = "event=0x7,instance=0x47,umask=0x2" },
155 	{ .name = "cake0_pcsout_txmeta",
156 			.config = "event=0x7,instance=0x46,umask=0x4" },
157 	{ .name = "cake1_pcsout_txmeta",
158 			.config = "event=0x7,instance=0x47,umask=0x4" },
159 	{ .name = "cake0_ftiinstat_reqalloc",
160 			.config = "event=0xb,instance=0x46,umask=0x4" },
161 	{ .name = "cake1_ftiinstat_reqalloc",
162 			.config = "event=0xb,instance=0x47,umask=0x4" },
163 	{ .name = "cake0_ftiinstat_rspalloc",
164 			.config = "event=0xb,instance=0x46,umask=0x8" },
165 	{ .name = "cake1_ftiinstat_rspalloc",
166 			.config = "event=0xb,instance=0x47,umask=0x8" }
180 	{ .name = "xgmi_link0_data_outbound",
181 			.config = "event=0x7,instance=0x4b,umask=0x2" },
182 	{ .name = "xgmi_link1_data_outbound",
183 			.config = "event=0x7,instance=0x4c,umask=0x2" },
184 	{ .name = "xgmi_link2_data_outbound",
185 			.config = "event=0x7,instance=0x4d,umask=0x2" },
186 	{ .name = "xgmi_link3_data_outbound",
187 			.config = "event=0x7,instance=0x4e,umask=0x2" },
188 	{ .name = "xgmi_link4_data_outbound",
189 			.config = "event=0x7,instance=0x4f,umask=0x2" },
190 	{ .name = "xgmi_link5_data_outbound",
191 			.config = "event=0x7,instance=0x50,umask=0x2" }
209 static int amdgpu_perf_event_init(struct perf_event *event)  in amdgpu_perf_event_init()  argument
211 	struct hw_perf_event *hwc = &event->hw;  in amdgpu_perf_event_init()
213 	/* test the event attr type check for PMU enumeration */  in amdgpu_perf_event_init()
214 	if (event->attr.type != event->pmu->type)  in amdgpu_perf_event_init()
215 		return -ENOENT;  in amdgpu_perf_event_init()
218 	hwc->config = event->attr.config;  in amdgpu_perf_event_init()
219 	hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE;  in amdgpu_perf_event_init()
225 static void amdgpu_perf_start(struct perf_event *event, int flags)  in amdgpu_perf_start()  argument
227 	struct hw_perf_event *hwc = &event->hw;  in amdgpu_perf_start()
228 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,  in amdgpu_perf_start()
233 	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))  in amdgpu_perf_start()
236 	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in amdgpu_perf_start()
237 	hwc->state = 0;  in amdgpu_perf_start()
239 	switch (hwc->config_base) {  in amdgpu_perf_start()
243 			target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,  in amdgpu_perf_start()
244 						hwc->config, 0 /* unused */,  in amdgpu_perf_start()
249 			hwc->idx = target_cntr;  in amdgpu_perf_start()
252 		pe->adev->df.funcs->pmc_start(pe->adev, hwc->config,  in amdgpu_perf_start()
253 								hwc->idx, 0);  in amdgpu_perf_start()
259 	perf_event_update_userpage(event);  in amdgpu_perf_start()
263 static void amdgpu_perf_read(struct perf_event *event)  in amdgpu_perf_read()  argument
265 	struct hw_perf_event *hwc = &event->hw;  in amdgpu_perf_read()
266 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,  in amdgpu_perf_read()
272 		prev = local64_read(&hwc->prev_count);  in amdgpu_perf_read()
274 		switch (hwc->config_base) {  in amdgpu_perf_read()
277 			pe->adev->df.funcs->pmc_get_count(pe->adev,  in amdgpu_perf_read()
278 						hwc->config, hwc->idx, &count);  in amdgpu_perf_read()
284 	} while (local64_cmpxchg(&hwc->prev_count, prev, count) != prev);  in amdgpu_perf_read()
286 	local64_add(count - prev, &event->count);  in amdgpu_perf_read()
290 static void amdgpu_perf_stop(struct perf_event *event, int flags)  in amdgpu_perf_stop()  argument
292 	struct hw_perf_event *hwc = &event->hw;  in amdgpu_perf_stop()
293 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,  in amdgpu_perf_stop()
297 	if (hwc->state & PERF_HES_UPTODATE)  in amdgpu_perf_stop()
300 	switch (hwc->config_base) {  in amdgpu_perf_stop()
303 		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,  in amdgpu_perf_stop()
310 	WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);  in amdgpu_perf_stop()
311 	hwc->state |= PERF_HES_STOPPED;  in amdgpu_perf_stop()
313 	if (hwc->state & PERF_HES_UPTODATE)  in amdgpu_perf_stop()
316 	amdgpu_perf_read(event);  in amdgpu_perf_stop()
317 	hwc->state |= PERF_HES_UPTODATE;  in amdgpu_perf_stop()
321 static int amdgpu_perf_add(struct perf_event *event, int flags)  in amdgpu_perf_add()  argument
323 	struct hw_perf_event *hwc = &event->hw;  in amdgpu_perf_add()
325 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,  in amdgpu_perf_add()
329 	switch (pe->pmu_perf_type) {  in amdgpu_perf_add()
331 		hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF;  in amdgpu_perf_add()
334 		hwc->config_base = (hwc->config >>  in amdgpu_perf_add()
340 	event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;  in amdgpu_perf_add()
342 	switch (hwc->config_base) {  in amdgpu_perf_add()
345 		target_cntr = pe->adev->df.funcs->pmc_start(pe->adev,  in amdgpu_perf_add()
346 						hwc->config, 0 /* unused */,  in amdgpu_perf_add()
351 			hwc->idx = target_cntr;  in amdgpu_perf_add()
362 		amdgpu_perf_start(event, PERF_EF_RELOAD);  in amdgpu_perf_add()
368 static void amdgpu_perf_del(struct perf_event *event, int flags)  in amdgpu_perf_del()  argument
370 	struct hw_perf_event *hwc = &event->hw;  in amdgpu_perf_del()
371 	struct amdgpu_pmu_entry *pe = container_of(event->pmu,  in amdgpu_perf_del()
375 	amdgpu_perf_stop(event, PERF_EF_UPDATE);  in amdgpu_perf_del()
377 	switch (hwc->config_base) {  in amdgpu_perf_del()
380 		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, hwc->idx,  in amdgpu_perf_del()
387 	perf_event_update_userpage(event);  in amdgpu_perf_del()
403 		attr_group->attrs[i] = &pmu_attr->attr.attr;  in amdgpu_pmu_create_event_attrs_by_type()
404 		sysfs_attr_init(&pmu_attr->attr.attr);  in amdgpu_pmu_create_event_attrs_by_type()
405 		pmu_attr->attr.attr.name = events[i].name;  in amdgpu_pmu_create_event_attrs_by_type()
406 		pmu_attr->attr.attr.mode = 0444;  in amdgpu_pmu_create_event_attrs_by_type()
407 		pmu_attr->attr.show = amdgpu_pmu_event_show;  in amdgpu_pmu_create_event_attrs_by_type()
408 		pmu_attr->event_str = events[i].config;  in amdgpu_pmu_create_event_attrs_by_type()
409 		pmu_attr->type = type;  in amdgpu_pmu_create_event_attrs_by_type()
431 	*fmt_attr = kcalloc(config->num_formats, sizeof(**fmt_attr),  in amdgpu_pmu_alloc_pmu_attrs()
435 		return -ENOMEM;  in amdgpu_pmu_alloc_pmu_attrs()
437 	fmt_attr_group->attrs = kcalloc(config->num_formats + 1,  in amdgpu_pmu_alloc_pmu_attrs()
438 				sizeof(*fmt_attr_group->attrs), GFP_KERNEL);  in amdgpu_pmu_alloc_pmu_attrs()
440 	if (!fmt_attr_group->attrs)  in amdgpu_pmu_alloc_pmu_attrs()
443 	*evt_attr = kcalloc(config->num_events, sizeof(**evt_attr), GFP_KERNEL);  in amdgpu_pmu_alloc_pmu_attrs()
448 	evt_attr_group->attrs = kcalloc(config->num_events + 1,  in amdgpu_pmu_alloc_pmu_attrs()
449 				sizeof(*evt_attr_group->attrs), GFP_KERNEL);  in amdgpu_pmu_alloc_pmu_attrs()
451 	if (!evt_attr_group->attrs)  in amdgpu_pmu_alloc_pmu_attrs()
458 	kfree(fmt_attr_group->attrs);  in amdgpu_pmu_alloc_pmu_attrs()
461 	return -ENOMEM;  in amdgpu_pmu_alloc_pmu_attrs()
469 		&pmu_entry->fmt_attr_group,  in init_pmu_entry_by_type_and_add()
470 		&pmu_entry->evt_attr_group,  in init_pmu_entry_by_type_and_add()
476 	pmu_entry->pmu = (struct pmu){  in init_pmu_entry_by_type_and_add()
486 	ret = amdgpu_pmu_alloc_pmu_attrs(&pmu_entry->fmt_attr_group,  in init_pmu_entry_by_type_and_add()
487 					&pmu_entry->fmt_attr,  in init_pmu_entry_by_type_and_add()
488 					&pmu_entry->evt_attr_group,  in init_pmu_entry_by_type_and_add()
489 					&pmu_entry->evt_attr,  in init_pmu_entry_by_type_and_add()
495 	amdgpu_pmu_create_attrs(&pmu_entry->fmt_attr_group, pmu_entry->fmt_attr,  in init_pmu_entry_by_type_and_add()
496 					config->formats, config->num_formats);  in init_pmu_entry_by_type_and_add()
498 	if (pmu_entry->pmu_perf_type == AMDGPU_PMU_PERF_TYPE_ALL) {  in init_pmu_entry_by_type_and_add()
501 		for (i = 0; i < config->num_types; i++) {  in init_pmu_entry_by_type_and_add()
503 					&pmu_entry->evt_attr_group,  in init_pmu_entry_by_type_and_add()
504 					pmu_entry->evt_attr,  in init_pmu_entry_by_type_and_add()
505 					config->events,  in init_pmu_entry_by_type_and_add()
508 						config->types[i].num_of_type,  in init_pmu_entry_by_type_and_add()
509 					config->types[i].type);  in init_pmu_entry_by_type_and_add()
510 			total_num_events += config->types[i].num_of_type;  in init_pmu_entry_by_type_and_add()
513 		amdgpu_pmu_create_attrs(&pmu_entry->evt_attr_group,  in init_pmu_entry_by_type_and_add()
514 					pmu_entry->evt_attr,  in init_pmu_entry_by_type_and_add()
515 					config->events, config->num_events);  in init_pmu_entry_by_type_and_add()
516 		total_num_events = config->num_events;  in init_pmu_entry_by_type_and_add()
519 	pmu_entry->pmu.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),  in init_pmu_entry_by_type_and_add()
522 	if (!pmu_entry->pmu.attr_groups) {  in init_pmu_entry_by_type_and_add()
523 		ret = -ENOMEM;  in init_pmu_entry_by_type_and_add()
527 	snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d", pmu_entry->pmu_file_prefix,  in init_pmu_entry_by_type_and_add()
528 				adev_to_drm(pmu_entry->adev)->primary->index);  in init_pmu_entry_by_type_and_add()
530 	ret = perf_pmu_register(&pmu_entry->pmu, pmu_name, -1);  in init_pmu_entry_by_type_and_add()
535 	if (pmu_entry->pmu_perf_type != AMDGPU_PMU_PERF_TYPE_ALL)  in init_pmu_entry_by_type_and_add()
537 				pmu_entry->pmu_type_name, total_num_events);  in init_pmu_entry_by_type_and_add()
542 	list_add_tail(&pmu_entry->entry, &amdgpu_pmu_list);  in init_pmu_entry_by_type_and_add()
546 	kfree(pmu_entry->pmu.attr_groups);  in init_pmu_entry_by_type_and_add()
548 	kfree(pmu_entry->fmt_attr_group.attrs);  in init_pmu_entry_by_type_and_add()
549 	kfree(pmu_entry->fmt_attr);  in init_pmu_entry_by_type_and_add()
550 	kfree(pmu_entry->evt_attr_group.attrs);  in init_pmu_entry_by_type_and_add()
551 	kfree(pmu_entry->evt_attr);  in init_pmu_entry_by_type_and_add()
554 						pmu_entry->pmu_type_name);  in init_pmu_entry_by_type_and_add()
564 		if (pe->adev != adev)  in amdgpu_pmu_fini()
566 		list_del(&pe->entry);  in amdgpu_pmu_fini()
567 		perf_pmu_unregister(&pe->pmu);  in amdgpu_pmu_fini()
568 		kfree(pe->pmu.attr_groups);  in amdgpu_pmu_fini()
569 		kfree(pe->fmt_attr_group.attrs);  in amdgpu_pmu_fini()
570 		kfree(pe->fmt_attr);  in amdgpu_pmu_fini()
571 		kfree(pe->evt_attr_group.attrs);  in amdgpu_pmu_fini()
572 		kfree(pe->evt_attr);  in amdgpu_pmu_fini()
589 	pmu_entry->adev = adev;  in create_pmu_entry()
590 	pmu_entry->fmt_attr_group.name = "format";  in create_pmu_entry()
591 	pmu_entry->fmt_attr_group.attrs = NULL;  in create_pmu_entry()
592 	pmu_entry->evt_attr_group.name = "events";  in create_pmu_entry()
593 	pmu_entry->evt_attr_group.attrs = NULL;  in create_pmu_entry()
594 	pmu_entry->pmu_perf_type = pmu_type;  in create_pmu_entry()
595 	pmu_entry->pmu_type_name = pmu_type_name;  in create_pmu_entry()
596 	pmu_entry->pmu_file_prefix = pmu_file_prefix;  in create_pmu_entry()
607 	switch (adev->asic_type) {  in amdgpu_pmu_init()
613 			return -ENOMEM;  in amdgpu_pmu_init()
628 			return -ENOMEM;  in amdgpu_pmu_init()
645 			return -ENOMEM;  in amdgpu_pmu_init()
652 			return -ENOMEM;  in amdgpu_pmu_init()