33  * amdgpu_pll_reduce_ratio - fractional number reduction
70  * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
74  * @post_div: post divider
80  * Calculate feedback and reference divider for a given post divider. Makes
89 	/* limit reference * post divider to a maximum */  in amdgpu_pll_get_fb_ref_div()
90 	if (adev->family == AMDGPU_FAMILY_SI)  in amdgpu_pll_get_fb_ref_div()
107  * amdgpu_pll_compute - compute PLL paramaters
129 	unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ?  in amdgpu_pll_compute()
139 	fb_div_min = pll->min_feedback_div;  in amdgpu_pll_compute()
140 	fb_div_max = pll->max_feedback_div;  in amdgpu_pll_compute()
142 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {  in amdgpu_pll_compute()
148 	if (pll->flags & AMDGPU_PLL_USE_REF_DIV)  in amdgpu_pll_compute()
149 		ref_div_min = pll->reference_div;  in amdgpu_pll_compute()
151 		ref_div_min = pll->min_ref_div;  in amdgpu_pll_compute()
153 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV &&  in amdgpu_pll_compute()
154 	    pll->flags & AMDGPU_PLL_USE_REF_DIV)  in amdgpu_pll_compute()
155 		ref_div_max = pll->reference_div;  in amdgpu_pll_compute()
157 		ref_div_max = pll->max_ref_div;  in amdgpu_pll_compute()
159 	/* determine allowed post divider range */  in amdgpu_pll_compute()
160 	if (pll->flags & AMDGPU_PLL_USE_POST_DIV) {  in amdgpu_pll_compute()
161 		post_div_min = pll->post_div;  in amdgpu_pll_compute()
162 		post_div_max = pll->post_div;  in amdgpu_pll_compute()
166 		if (pll->flags & AMDGPU_PLL_IS_LCD) {  in amdgpu_pll_compute()
167 			vco_min = pll->lcd_pll_out_min;  in amdgpu_pll_compute()
168 			vco_max = pll->lcd_pll_out_max;  in amdgpu_pll_compute()
170 			vco_min = pll->pll_out_min;  in amdgpu_pll_compute()
171 			vco_max = pll->pll_out_max;  in amdgpu_pll_compute()
174 		if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {  in amdgpu_pll_compute()
182 		if (post_div_min < pll->min_post_div)  in amdgpu_pll_compute()
183 			post_div_min = pll->min_post_div;  in amdgpu_pll_compute()
187 			--post_div_max;  in amdgpu_pll_compute()
188 		if (post_div_max > pll->max_post_div)  in amdgpu_pll_compute()
189 			post_div_max = pll->max_post_div;  in amdgpu_pll_compute()
194 	den = pll->reference_freq;  in amdgpu_pll_compute()
199 	/* now search for a post divider */  in amdgpu_pll_compute()
200 	if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP)  in amdgpu_pll_compute()
210 		diff = abs(target_clock - (pll->reference_freq * fb_div) /  in amdgpu_pll_compute()
214 		    !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) {  in amdgpu_pll_compute()
231 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {  in amdgpu_pll_compute()
232 		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);  in amdgpu_pll_compute()
241 	if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) {  in amdgpu_pll_compute()
249 	*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +  in amdgpu_pll_compute()
250 			(pll->reference_freq * *frac_fb_div_p)) /  in amdgpu_pll_compute()
255 	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",  in amdgpu_pll_compute()
261  * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use
269 	struct drm_device *dev = crtc->dev;  in amdgpu_pll_get_use_mask()
274 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {  in amdgpu_pll_get_use_mask()
279 		if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)  in amdgpu_pll_get_use_mask()
280 			pll_in_use |= (1 << test_amdgpu_crtc->pll_id);  in amdgpu_pll_get_use_mask()
286  * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP
296 	struct drm_device *dev = crtc->dev;  in amdgpu_pll_get_shared_dp_ppll()
300 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {  in amdgpu_pll_get_shared_dp_ppll()
304 		if (test_amdgpu_crtc->encoder &&  in amdgpu_pll_get_shared_dp_ppll()
305 		    ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {  in amdgpu_pll_get_shared_dp_ppll()
307 			if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)  in amdgpu_pll_get_shared_dp_ppll()
308 				return test_amdgpu_crtc->pll_id;  in amdgpu_pll_get_shared_dp_ppll()
315  * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
319  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
325 	struct drm_device *dev = crtc->dev;  in amdgpu_pll_get_shared_nondp_ppll()
330 	adjusted_clock = amdgpu_crtc->adjusted_clock;  in amdgpu_pll_get_shared_nondp_ppll()
335 	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {  in amdgpu_pll_get_shared_nondp_ppll()
339 		if (test_amdgpu_crtc->encoder &&  in amdgpu_pll_get_shared_nondp_ppll()
340 		    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) {  in amdgpu_pll_get_shared_nondp_ppll()
342 			if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) {  in amdgpu_pll_get_shared_nondp_ppll()
344 				if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)  in amdgpu_pll_get_shared_nondp_ppll()
345 					return test_amdgpu_crtc->pll_id;  in amdgpu_pll_get_shared_nondp_ppll()
347 			/* for non-DP check the clock */  in amdgpu_pll_get_shared_nondp_ppll()
348 			test_adjusted_clock = test_amdgpu_crtc->adjusted_clock;  in amdgpu_pll_get_shared_nondp_ppll()
349 			if ((crtc->mode.clock == test_crtc->mode.clock) &&  in amdgpu_pll_get_shared_nondp_ppll()
351 			    (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) &&  in amdgpu_pll_get_shared_nondp_ppll()
352 			    (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))  in amdgpu_pll_get_shared_nondp_ppll()
353 				return test_amdgpu_crtc->pll_id;  in amdgpu_pll_get_shared_nondp_ppll()