Lines Matching refs:resv
249 bp.resv = NULL; in amdgpu_bo_create_reserved()
533 .resv = bp->resv in amdgpu_bo_create()
591 bp->resv, bp->destroy); in amdgpu_bo_create()
607 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); in amdgpu_bo_create()
616 if (!bp->resv) in amdgpu_bo_create()
629 if (!bp->resv) in amdgpu_bo_create()
630 dma_resv_unlock(bo->tbo.base.resv); in amdgpu_bo_create()
801 r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false, in amdgpu_bo_kmap()
1158 dma_resv_assert_held(bo->tbo.base.resv); in amdgpu_bo_get_tiling_flags()
1338 && bo->base.resv != &bo->base._resv); in amdgpu_bo_release_notify()
1339 if (bo->base.resv == &bo->base._resv) in amdgpu_bo_release_notify()
1346 dma_resv_lock(bo->base.resv, NULL); in amdgpu_bo_release_notify()
1348 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); in amdgpu_bo_release_notify()
1354 dma_resv_unlock(bo->base.resv); in amdgpu_bo_release_notify()
1426 struct dma_resv *resv = bo->tbo.base.resv; in amdgpu_bo_fence() local
1429 dma_resv_add_shared_fence(resv, fence); in amdgpu_bo_fence()
1431 dma_resv_add_excl_fence(resv, fence); in amdgpu_bo_fence()
1448 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, in amdgpu_bo_sync_wait_resv() argument
1456 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); in amdgpu_bo_sync_wait_resv()
1476 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, in amdgpu_bo_sync_wait()
1493 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && in amdgpu_bo_gpu_offset()