Lines Matching refs:amdgpu_device

209 	int (*ras_late_init)(struct amdgpu_device *adev);
210 	void (*ras_fini)(struct amdgpu_device *adev);
211 	int (*ras_error_inject)(struct amdgpu_device *adev,
213 	int (*query_ras_error_count)(struct amdgpu_device *adev,
215 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
216 	void (*query_ras_error_status)(struct amdgpu_device *adev);
217 	void (*reset_ras_error_status)(struct amdgpu_device *adev);
218 	void (*enable_watchdog_timer)(struct amdgpu_device *adev);
223 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
224 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
226 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
228 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
231 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
234 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
236 	void (*init_spm_golden)(struct amdgpu_device *adev);
237 	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
362 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
363 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
368 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
374 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
375 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
378 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
380 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
381 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
382 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
384 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
385 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
387 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
389 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
391 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
393 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
395 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
397 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
399 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
401 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
402 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
403 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
404 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
405 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
408 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
411 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
412 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
413 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
414 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);