Lines Matching +full:dma +full:- +full:router
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
51 schedule_work(&work->flip_work.work); in amdgpu_display_flip_callback()
64 if (!dma_fence_add_callback(fence, &work->cb, in amdgpu_display_flip_handle_fence()
78 struct amdgpu_device *adev = work->adev; in amdgpu_display_flip_work_func()
79 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; in amdgpu_display_flip_work_func()
81 struct drm_crtc *crtc = &amdgpu_crtc->base; in amdgpu_display_flip_work_func()
86 if (amdgpu_display_flip_handle_fence(work, &work->excl)) in amdgpu_display_flip_work_func()
89 for (i = 0; i < work->shared_count; ++i) in amdgpu_display_flip_work_func()
90 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) in amdgpu_display_flip_work_func()
96 if (amdgpu_crtc->enabled && in amdgpu_display_flip_work_func()
97 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, in amdgpu_display_flip_work_func()
99 &crtc->hwmode) in amdgpu_display_flip_work_func()
102 (int)(work->target_vblank - in amdgpu_display_flip_work_func()
104 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); in amdgpu_display_flip_work_func()
109 spin_lock_irqsave(&crtc->dev->event_lock, flags); in amdgpu_display_flip_work_func()
112 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); in amdgpu_display_flip_work_func()
115 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; in amdgpu_display_flip_work_func()
116 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in amdgpu_display_flip_work_func()
120 amdgpu_crtc->crtc_id, amdgpu_crtc, work); in amdgpu_display_flip_work_func()
134 r = amdgpu_bo_reserve(work->old_abo, true); in amdgpu_display_unpin_work_func()
136 amdgpu_bo_unpin(work->old_abo); in amdgpu_display_unpin_work_func()
137 amdgpu_bo_unreserve(work->old_abo); in amdgpu_display_unpin_work_func()
141 amdgpu_bo_unref(&work->old_abo); in amdgpu_display_unpin_work_func()
142 kfree(work->shared); in amdgpu_display_unpin_work_func()
152 struct drm_device *dev = crtc->dev; in amdgpu_display_crtc_page_flip_target()
164 return -ENOMEM; in amdgpu_display_crtc_page_flip_target()
166 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); in amdgpu_display_crtc_page_flip_target()
167 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); in amdgpu_display_crtc_page_flip_target()
169 work->event = event; in amdgpu_display_crtc_page_flip_target()
170 work->adev = adev; in amdgpu_display_crtc_page_flip_target()
171 work->crtc_id = amdgpu_crtc->crtc_id; in amdgpu_display_crtc_page_flip_target()
172 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; in amdgpu_display_crtc_page_flip_target()
175 obj = crtc->primary->fb->obj[0]; in amdgpu_display_crtc_page_flip_target()
178 work->old_abo = gem_to_amdgpu_bo(obj); in amdgpu_display_crtc_page_flip_target()
179 amdgpu_bo_ref(work->old_abo); in amdgpu_display_crtc_page_flip_target()
181 obj = fb->obj[0]; in amdgpu_display_crtc_page_flip_target()
191 if (!adev->enable_virtual_display) { in amdgpu_display_crtc_page_flip_target()
193 amdgpu_display_supported_domains(adev, new_abo->flags)); in amdgpu_display_crtc_page_flip_target()
200 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); in amdgpu_display_crtc_page_flip_target()
206 r = dma_resv_get_fences(new_abo->tbo.base.resv, &work->excl, in amdgpu_display_crtc_page_flip_target()
207 &work->shared_count, &work->shared); in amdgpu_display_crtc_page_flip_target()
216 if (!adev->enable_virtual_display) in amdgpu_display_crtc_page_flip_target()
217 work->base = amdgpu_bo_gpu_offset(new_abo); in amdgpu_display_crtc_page_flip_target()
218 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + in amdgpu_display_crtc_page_flip_target()
222 spin_lock_irqsave(&crtc->dev->event_lock, flags); in amdgpu_display_crtc_page_flip_target()
223 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { in amdgpu_display_crtc_page_flip_target()
225 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in amdgpu_display_crtc_page_flip_target()
226 r = -EBUSY; in amdgpu_display_crtc_page_flip_target()
230 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; in amdgpu_display_crtc_page_flip_target()
231 amdgpu_crtc->pflip_works = work; in amdgpu_display_crtc_page_flip_target()
235 amdgpu_crtc->crtc_id, amdgpu_crtc, work); in amdgpu_display_crtc_page_flip_target()
237 crtc->primary->fb = fb; in amdgpu_display_crtc_page_flip_target()
238 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in amdgpu_display_crtc_page_flip_target()
239 amdgpu_display_flip_work_func(&work->flip_work.work); in amdgpu_display_crtc_page_flip_target()
248 if (!adev->enable_virtual_display) in amdgpu_display_crtc_page_flip_target()
255 amdgpu_bo_unref(&work->old_abo); in amdgpu_display_crtc_page_flip_target()
256 dma_fence_put(work->excl); in amdgpu_display_crtc_page_flip_target()
257 for (i = 0; i < work->shared_count; ++i) in amdgpu_display_crtc_page_flip_target()
258 dma_fence_put(work->shared[i]); in amdgpu_display_crtc_page_flip_target()
259 kfree(work->shared); in amdgpu_display_crtc_page_flip_target()
274 if (!set || !set->crtc) in amdgpu_display_crtc_set_config()
275 return -EINVAL; in amdgpu_display_crtc_set_config()
277 dev = set->crtc->dev; in amdgpu_display_crtc_set_config()
279 ret = pm_runtime_get_sync(dev->dev); in amdgpu_display_crtc_set_config()
285 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) in amdgpu_display_crtc_set_config()
286 if (crtc->enabled) in amdgpu_display_crtc_set_config()
289 pm_runtime_mark_last_busy(dev->dev); in amdgpu_display_crtc_set_config()
294 if (active && !adev->have_disp_power_ref) { in amdgpu_display_crtc_set_config()
295 adev->have_disp_power_ref = true; in amdgpu_display_crtc_set_config()
300 if (!active && adev->have_disp_power_ref) { in amdgpu_display_crtc_set_config()
301 pm_runtime_put_autosuspend(dev->dev); in amdgpu_display_crtc_set_config()
302 adev->have_disp_power_ref = false; in amdgpu_display_crtc_set_config()
307 pm_runtime_put_autosuspend(dev->dev); in amdgpu_display_crtc_set_config()
379 DRM_INFO(" %s\n", connector->name); in amdgpu_display_print_display_setup()
380 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) in amdgpu_display_print_display_setup()
381 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); in amdgpu_display_print_display_setup()
382 if (amdgpu_connector->ddc_bus) { in amdgpu_display_print_display_setup()
384 amdgpu_connector->ddc_bus->rec.mask_clk_reg, in amdgpu_display_print_display_setup()
385 amdgpu_connector->ddc_bus->rec.mask_data_reg, in amdgpu_display_print_display_setup()
386 amdgpu_connector->ddc_bus->rec.a_clk_reg, in amdgpu_display_print_display_setup()
387 amdgpu_connector->ddc_bus->rec.a_data_reg, in amdgpu_display_print_display_setup()
388 amdgpu_connector->ddc_bus->rec.en_clk_reg, in amdgpu_display_print_display_setup()
389 amdgpu_connector->ddc_bus->rec.en_data_reg, in amdgpu_display_print_display_setup()
390 amdgpu_connector->ddc_bus->rec.y_clk_reg, in amdgpu_display_print_display_setup()
391 amdgpu_connector->ddc_bus->rec.y_data_reg); in amdgpu_display_print_display_setup()
392 if (amdgpu_connector->router.ddc_valid) in amdgpu_display_print_display_setup()
393 DRM_INFO(" DDC Router 0x%x/0x%x\n", in amdgpu_display_print_display_setup()
394 amdgpu_connector->router.ddc_mux_control_pin, in amdgpu_display_print_display_setup()
395 amdgpu_connector->router.ddc_mux_state); in amdgpu_display_print_display_setup()
396 if (amdgpu_connector->router.cd_valid) in amdgpu_display_print_display_setup()
397 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", in amdgpu_display_print_display_setup()
398 amdgpu_connector->router.cd_mux_control_pin, in amdgpu_display_print_display_setup()
399 amdgpu_connector->router.cd_mux_state); in amdgpu_display_print_display_setup()
401 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || in amdgpu_display_print_display_setup()
402 connector->connector_type == DRM_MODE_CONNECTOR_DVII || in amdgpu_display_print_display_setup()
403 connector->connector_type == DRM_MODE_CONNECTOR_DVID || in amdgpu_display_print_display_setup()
404 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || in amdgpu_display_print_display_setup()
405 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || in amdgpu_display_print_display_setup()
406 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) in amdgpu_display_print_display_setup()
407 …DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); in amdgpu_display_print_display_setup()
410 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in amdgpu_display_print_display_setup()
412 devices = amdgpu_encoder->devices & amdgpu_connector->devices; in amdgpu_display_print_display_setup()
415 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
417 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
419 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
421 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
423 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
425 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
427 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
429 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
431 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
433 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
435 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); in amdgpu_display_print_display_setup()
465 if (amdgpu_connector->router.ddc_valid) in amdgpu_display_ddc_probe()
469 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); in amdgpu_display_ddc_probe()
471 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); in amdgpu_display_ddc_probe()
511 amdgpu_device_asic_has_dc_support(adev->asic_type)) { in amdgpu_display_supported_domains()
512 switch (adev->asic_type) { in amdgpu_display_supported_domains()
519 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || in amdgpu_display_supported_domains()
520 (adev->apu_flags & AMD_APU_IS_PICASSO)) in amdgpu_display_supported_domains()
646 /* Don't show error message when returning -ERESTARTSYS */ in extract_render_dcc_offset()
647 if (r != -ERESTARTSYS) in extract_render_dcc_offset()
663 return -EINVAL; in extract_render_dcc_offset()
665 if (adev->family >= AMDGPU_FAMILY_NV) { in extract_render_dcc_offset()
680 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); in convert_tiling_flags_to_modifier()
683 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
686 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
694 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in convert_tiling_flags_to_modifier()
695 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier()
712 return -EINVAL; in convert_tiling_flags_to_modifier()
715 if (adev->asic_type >= CHIP_SIENNA_CICHLID) in convert_tiling_flags_to_modifier()
717 else if (adev->family == AMDGPU_FAMILY_NV) in convert_tiling_flags_to_modifier()
724 return -EINVAL; in convert_tiling_flags_to_modifier()
730 if (!has_xor && afb->base.format->cpp[0] != 4) in convert_tiling_flags_to_modifier()
740 pipe_xor_bits = min(block_size_bits - 8, pipes); in convert_tiling_flags_to_modifier()
741 packers = min(block_size_bits - 8 - pipe_xor_bits, in convert_tiling_flags_to_modifier()
742 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); in convert_tiling_flags_to_modifier()
745 pipe_xor_bits = min(block_size_bits - 8, pipes); in convert_tiling_flags_to_modifier()
748 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()
749 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in convert_tiling_flags_to_modifier()
750 pipe_xor_bits = min(block_size_bits - 8, pipes + in convert_tiling_flags_to_modifier()
751 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()
752 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, in convert_tiling_flags_to_modifier()
753 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in convert_tiling_flags_to_modifier()
759 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier()
766 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier()
772 bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN || in convert_tiling_flags_to_modifier()
773 (adev->asic_type == CHIP_RAVEN && in convert_tiling_flags_to_modifier()
774 adev->external_rev_id >= 0x81); in convert_tiling_flags_to_modifier()
786 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; in convert_tiling_flags_to_modifier()
787 afb->base.pitches[1] = in convert_tiling_flags_to_modifier()
788 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
798 if (extract_render_dcc_offset(adev, afb->base.obj[0], in convert_tiling_flags_to_modifier()
801 render_dcc_offset != afb->base.offsets[1] && in convert_tiling_flags_to_modifier()
806 afb->base.offsets[2] = render_dcc_offset; in convert_tiling_flags_to_modifier()
808 if (adev->family >= AMDGPU_FAMILY_NV) { in convert_tiling_flags_to_modifier()
811 if (adev->asic_type >= CHIP_SIENNA_CICHLID && in convert_tiling_flags_to_modifier()
822 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); in convert_tiling_flags_to_modifier()
823 afb->base.pitches[2] = ALIGN(afb->base.width, in convert_tiling_flags_to_modifier()
826 format_info = amdgpu_lookup_format_info(afb->base.format->format, in convert_tiling_flags_to_modifier()
829 return -EINVAL; in convert_tiling_flags_to_modifier()
831 afb->base.format = format_info; in convert_tiling_flags_to_modifier()
835 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier()
836 afb->base.flags |= DRM_MODE_FB_MODIFIERS; in convert_tiling_flags_to_modifier()
846 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) in check_tiling_flags_gfx6()
849 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); in check_tiling_flags_gfx6()
855 drm_dbg_kms(afb->base.dev, in check_tiling_flags_gfx6()
858 return -EINVAL; in check_tiling_flags_gfx6()
866 unsigned int pixel_log2 = block_log2 - cpp_log2; in get_block_dimensions()
868 unsigned int height_log2 = pixel_log2 - width_log2; in get_block_dimensions()
908 unsigned int width = rfb->base.width / in amdgpu_display_verify_plane()
909 ((plane && plane < format->num_planes) ? format->hsub : 1); in amdgpu_display_verify_plane()
910 unsigned int height = rfb->base.height / in amdgpu_display_verify_plane()
911 ((plane && plane < format->num_planes) ? format->vsub : 1); in amdgpu_display_verify_plane()
912 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; in amdgpu_display_verify_plane()
918 if (rfb->base.pitches[plane] % block_pitch) { in amdgpu_display_verify_plane()
919 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
921 rfb->base.pitches[plane], plane, block_pitch); in amdgpu_display_verify_plane()
922 return -EINVAL; in amdgpu_display_verify_plane()
924 if (rfb->base.pitches[plane] < min_pitch) { in amdgpu_display_verify_plane()
925 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
927 rfb->base.pitches[plane], plane, min_pitch); in amdgpu_display_verify_plane()
928 return -EINVAL; in amdgpu_display_verify_plane()
932 if (rfb->base.offsets[plane] % block_size) { in amdgpu_display_verify_plane()
933 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
935 rfb->base.offsets[plane], plane, block_size); in amdgpu_display_verify_plane()
936 return -EINVAL; in amdgpu_display_verify_plane()
939 size = rfb->base.offsets[plane] + in amdgpu_display_verify_plane()
940 (uint64_t)rfb->base.pitches[plane] / block_pitch * in amdgpu_display_verify_plane()
943 if (rfb->base.obj[0]->size < size) { in amdgpu_display_verify_plane()
944 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_plane()
946 rfb->base.obj[0]->size, size, plane); in amdgpu_display_verify_plane()
947 return -EINVAL; in amdgpu_display_verify_plane()
956 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); in amdgpu_display_verify_sizes()
957 uint64_t modifier = rfb->base.modifier; in amdgpu_display_verify_sizes()
961 if (!rfb->base.dev->mode_config.allow_fb_modifiers) in amdgpu_display_verify_sizes()
964 for (i = 0; i < format_info->num_planes; ++i) { in amdgpu_display_verify_sizes()
966 block_width = 256 / format_info->cpp[i]; in amdgpu_display_verify_sizes()
986 drm_dbg_kms(rfb->base.dev, in amdgpu_display_verify_sizes()
988 return -EINVAL; in amdgpu_display_verify_sizes()
991 get_block_dimensions(block_size_log2, format_info->cpp[i], in amdgpu_display_verify_sizes()
1004 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], in amdgpu_display_verify_sizes()
1019 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], in amdgpu_display_verify_sizes()
1042 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); in amdgpu_display_get_fb_info()
1046 /* Don't show error message when returning -ERESTARTSYS */ in amdgpu_display_get_fb_info()
1047 if (r != -ERESTARTSYS) in amdgpu_display_get_fb_info()
1070 rfb->base.obj[0] = obj; in amdgpu_display_gem_fb_init()
1071 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); in amdgpu_display_gem_fb_init()
1077 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); in amdgpu_display_gem_fb_init()
1084 rfb->base.obj[0] = NULL; in amdgpu_display_gem_fb_init()
1095 rfb->base.obj[0] = obj; in amdgpu_display_gem_fb_verify_and_init()
1096 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); in amdgpu_display_gem_fb_verify_and_init()
1098 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, in amdgpu_display_gem_fb_verify_and_init()
1099 mode_cmd->modifier[0])) { in amdgpu_display_gem_fb_verify_and_init()
1102 &mode_cmd->pixel_format, mode_cmd->modifier[0]); in amdgpu_display_gem_fb_verify_and_init()
1104 ret = -EINVAL; in amdgpu_display_gem_fb_verify_and_init()
1112 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); in amdgpu_display_gem_fb_verify_and_init()
1119 rfb->base.obj[0] = NULL; in amdgpu_display_gem_fb_verify_and_init()
1135 for (i = 1; i < rfb->base.format->num_planes; ++i) { in amdgpu_display_framebuffer_init()
1136 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { in amdgpu_display_framebuffer_init()
1138 i, mode_cmd->handles[0], mode_cmd->handles[i]); in amdgpu_display_framebuffer_init()
1139 ret = -EINVAL; in amdgpu_display_framebuffer_init()
1144 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); in amdgpu_display_framebuffer_init()
1148 if (!dev->mode_config.allow_fb_modifiers) { in amdgpu_display_framebuffer_init()
1149 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, in amdgpu_display_framebuffer_init()
1156 if (dev->mode_config.allow_fb_modifiers && in amdgpu_display_framebuffer_init()
1157 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { in amdgpu_display_framebuffer_init()
1161 rfb->tiling_flags); in amdgpu_display_framebuffer_init()
1170 for (i = 0; i < rfb->base.format->num_planes; ++i) { in amdgpu_display_framebuffer_init()
1171 drm_gem_object_get(rfb->base.obj[0]); in amdgpu_display_framebuffer_init()
1172 rfb->base.obj[i] = rfb->base.obj[0]; in amdgpu_display_framebuffer_init()
1189 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); in amdgpu_display_user_framebuffer_create()
1192 "can't create framebuffer\n", mode_cmd->handles[0]); in amdgpu_display_user_framebuffer_create()
1193 return ERR_PTR(-ENOENT); in amdgpu_display_user_framebuffer_create()
1196 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ in amdgpu_display_user_framebuffer_create()
1198 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); in amdgpu_display_user_framebuffer_create()
1199 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { in amdgpu_display_user_framebuffer_create()
1202 return ERR_PTR(-EINVAL); in amdgpu_display_user_framebuffer_create()
1208 return ERR_PTR(-ENOMEM); in amdgpu_display_user_framebuffer_create()
1220 return &amdgpu_fb->base; in amdgpu_display_user_framebuffer_create()
1250 adev->mode_info.coherent_mode_property = in amdgpu_display_modeset_create_props()
1252 if (!adev->mode_info.coherent_mode_property) in amdgpu_display_modeset_create_props()
1253 return -ENOMEM; in amdgpu_display_modeset_create_props()
1255 adev->mode_info.load_detect_property = in amdgpu_display_modeset_create_props()
1257 if (!adev->mode_info.load_detect_property) in amdgpu_display_modeset_create_props()
1258 return -ENOMEM; in amdgpu_display_modeset_create_props()
1263 adev->mode_info.underscan_property = in amdgpu_display_modeset_create_props()
1268 adev->mode_info.underscan_hborder_property = in amdgpu_display_modeset_create_props()
1271 if (!adev->mode_info.underscan_hborder_property) in amdgpu_display_modeset_create_props()
1272 return -ENOMEM; in amdgpu_display_modeset_create_props()
1274 adev->mode_info.underscan_vborder_property = in amdgpu_display_modeset_create_props()
1277 if (!adev->mode_info.underscan_vborder_property) in amdgpu_display_modeset_create_props()
1278 return -ENOMEM; in amdgpu_display_modeset_create_props()
1281 adev->mode_info.audio_property = in amdgpu_display_modeset_create_props()
1287 adev->mode_info.dither_property = in amdgpu_display_modeset_create_props()
1293 adev->mode_info.abm_level_property = in amdgpu_display_modeset_create_props()
1296 if (!adev->mode_info.abm_level_property) in amdgpu_display_modeset_create_props()
1297 return -ENOMEM; in amdgpu_display_modeset_create_props()
1307 adev->mode_info.disp_priority = 0; in amdgpu_display_update_priority()
1309 adev->mode_info.disp_priority = amdgpu_disp_priority; in amdgpu_display_update_priority()
1316 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ in amdgpu_display_is_hdtv_mode()
1317 (mode->vdisplay == 576) || /* 576p */ in amdgpu_display_is_hdtv_mode()
1318 (mode->vdisplay == 720) || /* 720p */ in amdgpu_display_is_hdtv_mode()
1319 (mode->vdisplay == 1080)) /* 1080p */ in amdgpu_display_is_hdtv_mode()
1329 struct drm_device *dev = crtc->dev; in amdgpu_display_crtc_scaling_mode_fixup()
1337 amdgpu_crtc->h_border = 0; in amdgpu_display_crtc_scaling_mode_fixup()
1338 amdgpu_crtc->v_border = 0; in amdgpu_display_crtc_scaling_mode_fixup()
1340 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in amdgpu_display_crtc_scaling_mode_fixup()
1341 if (encoder->crtc != crtc) in amdgpu_display_crtc_scaling_mode_fixup()
1347 if (amdgpu_encoder->rmx_type == RMX_OFF) in amdgpu_display_crtc_scaling_mode_fixup()
1348 amdgpu_crtc->rmx_type = RMX_OFF; in amdgpu_display_crtc_scaling_mode_fixup()
1349 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || in amdgpu_display_crtc_scaling_mode_fixup()
1350 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) in amdgpu_display_crtc_scaling_mode_fixup()
1351 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; in amdgpu_display_crtc_scaling_mode_fixup()
1353 amdgpu_crtc->rmx_type = RMX_OFF; in amdgpu_display_crtc_scaling_mode_fixup()
1355 memcpy(&amdgpu_crtc->native_mode, in amdgpu_display_crtc_scaling_mode_fixup()
1356 &amdgpu_encoder->native_mode, in amdgpu_display_crtc_scaling_mode_fixup()
1358 src_v = crtc->mode.vdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1359 dst_v = amdgpu_crtc->native_mode.vdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1360 src_h = crtc->mode.hdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1361 dst_h = amdgpu_crtc->native_mode.hdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1364 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && in amdgpu_display_crtc_scaling_mode_fixup()
1365 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || in amdgpu_display_crtc_scaling_mode_fixup()
1366 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && in amdgpu_display_crtc_scaling_mode_fixup()
1369 if (amdgpu_encoder->underscan_hborder != 0) in amdgpu_display_crtc_scaling_mode_fixup()
1370 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; in amdgpu_display_crtc_scaling_mode_fixup()
1372 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; in amdgpu_display_crtc_scaling_mode_fixup()
1373 if (amdgpu_encoder->underscan_vborder != 0) in amdgpu_display_crtc_scaling_mode_fixup()
1374 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; in amdgpu_display_crtc_scaling_mode_fixup()
1376 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; in amdgpu_display_crtc_scaling_mode_fixup()
1377 amdgpu_crtc->rmx_type = RMX_FULL; in amdgpu_display_crtc_scaling_mode_fixup()
1378 src_v = crtc->mode.vdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1379 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); in amdgpu_display_crtc_scaling_mode_fixup()
1380 src_h = crtc->mode.hdisplay; in amdgpu_display_crtc_scaling_mode_fixup()
1381 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); in amdgpu_display_crtc_scaling_mode_fixup()
1384 if (amdgpu_crtc->rmx_type != RMX_OFF) { in amdgpu_display_crtc_scaling_mode_fixup()
1388 amdgpu_crtc->vsc.full = dfixed_div(a, b); in amdgpu_display_crtc_scaling_mode_fixup()
1391 amdgpu_crtc->hsc.full = dfixed_div(a, b); in amdgpu_display_crtc_scaling_mode_fixup()
1393 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
1394 amdgpu_crtc->hsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
1424 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1475 vbl_start = mode->crtc_vdisplay; in amdgpu_display_get_crtc_scanoutpos()
1482 *hpos = *vpos - vbl_start; in amdgpu_display_get_crtc_scanoutpos()
1496 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in amdgpu_display_get_crtc_scanoutpos()
1509 *vpos -= vbl_start; in amdgpu_display_get_crtc_scanoutpos()
1521 vtotal = mode->crtc_vtotal; in amdgpu_display_get_crtc_scanoutpos()
1524 * the vtotal value. Clamp to 0 to return -vbl_end instead in amdgpu_display_get_crtc_scanoutpos()
1527 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; in amdgpu_display_get_crtc_scanoutpos()
1531 *vpos = *vpos - vbl_end; in amdgpu_display_get_crtc_scanoutpos()
1538 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) in amdgpu_display_crtc_idx_to_irq_type()
1564 struct drm_device *dev = crtc->dev; in amdgpu_crtc_get_scanout_position()
1565 unsigned int pipe = crtc->index; in amdgpu_crtc_get_scanout_position()
1588 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in amdgpu_display_suspend_helper()
1590 struct drm_framebuffer *fb = crtc->primary->fb; in amdgpu_display_suspend_helper()
1593 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { in amdgpu_display_suspend_helper()
1594 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in amdgpu_display_suspend_helper()
1602 if (fb == NULL || fb->obj[0] == NULL) { in amdgpu_display_suspend_helper()
1605 robj = gem_to_amdgpu_bo(fb->obj[0]); in amdgpu_display_suspend_helper()
1627 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in amdgpu_display_resume_helper()
1630 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { in amdgpu_display_resume_helper()
1631 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in amdgpu_display_resume_helper()
1636 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); in amdgpu_display_resume_helper()
1637 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in amdgpu_display_resume_helper()