137  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
816  * Bits 23..30: CU/{WGP+SIMD} selector
830 	uint32_t offset, se, sh, cu, wave, simd, data[32];  in amdgpu_debugfs_wave_read()  local
839 	cu = (*pos & GENMASK_ULL(30, 23)) >> 23;  in amdgpu_debugfs_wave_read()
855 	/* switch to the specific se/sh/cu */  in amdgpu_debugfs_wave_read()
857 	amdgpu_gfx_select_se_sh(adev, se, sh, cu);  in amdgpu_debugfs_wave_read()
907  * Bits 28..35: CU/{WGP+SIMD} selector
922 	uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;  in amdgpu_debugfs_gpr_read()  local
931 	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;  in amdgpu_debugfs_gpr_read()
949 	/* switch to the specific se/sh/cu */  in amdgpu_debugfs_gpr_read()
951 	amdgpu_gfx_select_se_sh(adev, se, sh, cu);  in amdgpu_debugfs_gpr_read()