1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/gpio/driver.h>
47 	spin_lock_irqsave(&chip->gc.bgpio_lock, flags);  in sifive_gpio_set_ie()
48 	trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;  in sifive_gpio_set_ie()
49 	regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),  in sifive_gpio_set_ie()
51 	regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset),  in sifive_gpio_set_ie()
53 	regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset),  in sifive_gpio_set_ie()
55 	regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),  in sifive_gpio_set_ie()
57 	spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);  in sifive_gpio_set_ie()
66 	if (offset < 0 || offset >= gc->ngpio)  in sifive_gpio_irq_set_type()
67 		return -EINVAL;  in sifive_gpio_irq_set_type()
69 	chip->trigger[offset] = trigger;  in sifive_gpio_irq_set_type()
85 	gc->direction_input(gc, offset);  in sifive_gpio_irq_enable()
87 	spin_lock_irqsave(&gc->bgpio_lock, flags);  in sifive_gpio_irq_enable()
89 	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);  in sifive_gpio_irq_enable()
90 	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);  in sifive_gpio_irq_enable()
91 	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);  in sifive_gpio_irq_enable()
92 	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);  in sifive_gpio_irq_enable()
93 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in sifive_gpio_irq_enable()
96 	assign_bit(offset, &chip->irq_state, 1);  in sifive_gpio_irq_enable()
106 	assign_bit(offset, &chip->irq_state, 0);  in sifive_gpio_irq_disable()
119 	spin_lock_irqsave(&gc->bgpio_lock, flags);  in sifive_gpio_irq_eoi()
121 	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);  in sifive_gpio_irq_eoi()
122 	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);  in sifive_gpio_irq_eoi()
123 	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);  in sifive_gpio_irq_eoi()
124 	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);  in sifive_gpio_irq_eoi()
125 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in sifive_gpio_irq_eoi()
134 	if (data->parent_data)  in sifive_gpio_irq_set_affinity()
137 	return -EINVAL;  in sifive_gpio_irq_set_affinity()
141 	.name		= "sifive-gpio",
158 	struct irq_data *d = irq_get_irq_data(chip->irq_number[child]);  in sifive_gpio_child_to_parent_hwirq()
176 	struct device *dev = &pdev->dev;  in sifive_gpio_probe()
177 	struct device_node *node = pdev->dev.of_node;  in sifive_gpio_probe()
186 		return -ENOMEM;  in sifive_gpio_probe()
188 	chip->base = devm_platform_ioremap_resource(pdev, 0);  in sifive_gpio_probe()
189 	if (IS_ERR(chip->base)) {  in sifive_gpio_probe()
191 		return PTR_ERR(chip->base);  in sifive_gpio_probe()
194 	chip->regs = devm_regmap_init_mmio(dev, chip->base,  in sifive_gpio_probe()
196 	if (IS_ERR(chip->regs))  in sifive_gpio_probe()
197 		return PTR_ERR(chip->regs);  in sifive_gpio_probe()
201 		dev_err(dev, "Too many GPIO interrupts (max=%d)\n",  in sifive_gpio_probe()
203 		return -ENXIO;  in sifive_gpio_probe()
209 		return -ENODEV;  in sifive_gpio_probe()
214 		return -ENODEV;  in sifive_gpio_probe()
218 		chip->irq_number[i] = platform_get_irq(pdev, i);  in sifive_gpio_probe()
220 	ret = bgpio_init(&chip->gc, dev, 4,  in sifive_gpio_probe()
221 			 chip->base + SIFIVE_GPIO_INPUT_VAL,  in sifive_gpio_probe()
222 			 chip->base + SIFIVE_GPIO_OUTPUT_VAL,  in sifive_gpio_probe()
224 			 chip->base + SIFIVE_GPIO_OUTPUT_EN,  in sifive_gpio_probe()
225 			 chip->base + SIFIVE_GPIO_INPUT_EN,  in sifive_gpio_probe()
228 		dev_err(dev, "unable to init generic GPIO\n");  in sifive_gpio_probe()
232 	/* Disable all GPIO interrupts before enabling parent interrupts */  in sifive_gpio_probe()
233 	regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);  in sifive_gpio_probe()
234 	regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);  in sifive_gpio_probe()
235 	regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);  in sifive_gpio_probe()
236 	regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);  in sifive_gpio_probe()
237 	chip->irq_state = 0;  in sifive_gpio_probe()
239 	chip->gc.base = -1;  in sifive_gpio_probe()
240 	chip->gc.ngpio = ngpio;  in sifive_gpio_probe()
241 	chip->gc.label = dev_name(dev);  in sifive_gpio_probe()
242 	chip->gc.parent = dev;  in sifive_gpio_probe()
243 	chip->gc.owner = THIS_MODULE;  in sifive_gpio_probe()
244 	girq = &chip->gc.irq;  in sifive_gpio_probe()
245 	girq->chip = &sifive_gpio_irqchip;  in sifive_gpio_probe()
246 	girq->fwnode = of_node_to_fwnode(node);  in sifive_gpio_probe()
247 	girq->parent_domain = parent;  in sifive_gpio_probe()
248 	girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;  in sifive_gpio_probe()
249 	girq->handler = handle_bad_irq;  in sifive_gpio_probe()
250 	girq->default_type = IRQ_TYPE_NONE;  in sifive_gpio_probe()
253 	return gpiochip_add_data(&chip->gc, chip);  in sifive_gpio_probe()
258 	{ .compatible = "sifive,fu540-c000-gpio" },