Lines Matching +full:lock +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
27 #include <linux/platform_data/gpio-omap.h>
58 raw_spinlock_t lock; member
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
84 #define LINE_USED(line, offset) (line & (BIT(offset))) argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
121 u32 l = BIT(offset); in omap_set_gpio_dataout_reg()
124 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
125 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
127 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
128 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_mask() argument
138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, in omap_set_gpio_dataout_mask()
139 BIT(offset), enable); in omap_set_gpio_dataout_mask()
144 if (bank->dbck_enable_mask && !bank->dbck_enabled) { in omap_gpio_dbck_enable()
145 clk_enable(bank->dbck); in omap_gpio_dbck_enable()
146 bank->dbck_enabled = true; in omap_gpio_dbck_enable()
148 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable()
149 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable()
155 if (bank->dbck_enable_mask && bank->dbck_enabled) { in omap_gpio_dbck_disable()
161 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
163 clk_disable(bank->dbck); in omap_gpio_dbck_disable()
164 bank->dbck_enabled = false; in omap_gpio_dbck_disable()
169 * omap2_set_gpio_debounce - low level gpio debounce time
171 * @offset: the gpio number on this @bank
180 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, in omap2_set_gpio_debounce() argument
187 if (!bank->dbck_flag) in omap2_set_gpio_debounce()
188 return -ENOTSUPP; in omap2_set_gpio_debounce()
191 debounce = DIV_ROUND_UP(debounce, 31) - 1; in omap2_set_gpio_debounce()
193 return -EINVAL; in omap2_set_gpio_debounce()
196 l = BIT(offset); in omap2_set_gpio_debounce()
198 clk_enable(bank->dbck); in omap2_set_gpio_debounce()
199 writel_relaxed(debounce, bank->base + bank->regs->debounce); in omap2_set_gpio_debounce()
201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); in omap2_set_gpio_debounce()
202 bank->dbck_enable_mask = val; in omap2_set_gpio_debounce()
204 clk_disable(bank->dbck); in omap2_set_gpio_debounce()
214 if (bank->dbck_enable_mask) { in omap2_set_gpio_debounce()
215 bank->context.debounce = debounce; in omap2_set_gpio_debounce()
216 bank->context.debounce_en = val; in omap2_set_gpio_debounce()
223 * omap_clear_gpio_debounce - clear debounce settings for a gpio
225 * @offset: the gpio number on this @bank
232 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) in omap_clear_gpio_debounce() argument
234 u32 gpio_bit = BIT(offset); in omap_clear_gpio_debounce()
236 if (!bank->dbck_flag) in omap_clear_gpio_debounce()
239 if (!(bank->dbck_enable_mask & gpio_bit)) in omap_clear_gpio_debounce()
242 bank->dbck_enable_mask &= ~gpio_bit; in omap_clear_gpio_debounce()
243 bank->context.debounce_en &= ~gpio_bit; in omap_clear_gpio_debounce()
244 writel_relaxed(bank->context.debounce_en, in omap_clear_gpio_debounce()
245 bank->base + bank->regs->debounce_en); in omap_clear_gpio_debounce()
247 if (!bank->dbck_enable_mask) { in omap_clear_gpio_debounce()
248 bank->context.debounce = 0; in omap_clear_gpio_debounce()
249 writel_relaxed(bank->context.debounce, bank->base + in omap_clear_gpio_debounce()
250 bank->regs->debounce); in omap_clear_gpio_debounce()
251 clk_disable(bank->dbck); in omap_clear_gpio_debounce()
252 bank->dbck_enabled = false; in omap_clear_gpio_debounce()
257 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
258 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
259 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
264 u32 no_wake = bank->non_wakeup_gpios; in omap_gpio_is_off_wakeup_capable()
275 void __iomem *base = bank->base; in omap_set_gpio_trigger()
278 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, in omap_set_gpio_trigger()
280 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, in omap_set_gpio_trigger()
288 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, in omap_set_gpio_trigger()
290 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, in omap_set_gpio_trigger()
293 bank->context.leveldetect0 = in omap_set_gpio_trigger()
294 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
295 bank->context.leveldetect1 = in omap_set_gpio_trigger()
296 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
297 bank->context.risingdetect = in omap_set_gpio_trigger()
298 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
299 bank->context.fallingdetect = in omap_set_gpio_trigger()
300 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
302 bank->level_mask = bank->context.leveldetect0 | in omap_set_gpio_trigger()
303 bank->context.leveldetect1; in omap_set_gpio_trigger()
306 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { in omap_set_gpio_trigger()
311 * Applies for omap2 non-wakeup gpio and all omap3 gpios in omap_set_gpio_trigger()
314 bank->enabled_non_wakeup_gpios |= gpio_bit; in omap_set_gpio_trigger()
316 bank->enabled_non_wakeup_gpios &= ~gpio_bit; in omap_set_gpio_trigger()
326 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { in omap_toggle_gpio_edge_triggering()
327 void __iomem *reg = bank->base + bank->regs->irqctrl; in omap_toggle_gpio_edge_triggering()
336 void __iomem *reg = bank->base; in omap_set_gpio_triggering()
339 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { in omap_set_gpio_triggering()
341 } else if (bank->regs->irqctrl) { in omap_set_gpio_triggering()
342 reg += bank->regs->irqctrl; in omap_set_gpio_triggering()
346 bank->toggle_mask |= BIT(gpio); in omap_set_gpio_triggering()
352 return -EINVAL; in omap_set_gpio_triggering()
355 } else if (bank->regs->edgectrl1) { in omap_set_gpio_triggering()
357 reg += bank->regs->edgectrl2; in omap_set_gpio_triggering()
359 reg += bank->regs->edgectrl1; in omap_set_gpio_triggering()
373 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) in omap_enable_gpio_module() argument
375 if (bank->regs->pinctrl) { in omap_enable_gpio_module()
376 void __iomem *reg = bank->base + bank->regs->pinctrl; in omap_enable_gpio_module()
379 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); in omap_enable_gpio_module()
382 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_enable_gpio_module()
383 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_enable_gpio_module()
390 bank->context.ctrl = ctrl; in omap_enable_gpio_module()
394 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) in omap_disable_gpio_module() argument
396 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_disable_gpio_module()
397 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_disable_gpio_module()
404 bank->context.ctrl = ctrl; in omap_disable_gpio_module()
408 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) in omap_gpio_is_input() argument
410 void __iomem *reg = bank->base + bank->regs->direction; in omap_gpio_is_input()
412 return readl_relaxed(reg) & BIT(offset); in omap_gpio_is_input()
415 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) in omap_gpio_init_irq() argument
417 if (!LINE_USED(bank->mod_usage, offset)) { in omap_gpio_init_irq()
418 omap_enable_gpio_module(bank, offset); in omap_gpio_init_irq()
419 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_init_irq()
421 bank->irq_usage |= BIT(offset); in omap_gpio_init_irq()
429 unsigned offset = d->hwirq; in omap_gpio_irq_type() local
432 return -EINVAL; in omap_gpio_irq_type()
434 if (!bank->regs->leveldetect0 && in omap_gpio_irq_type()
436 return -EINVAL; in omap_gpio_irq_type()
438 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_type()
439 retval = omap_set_gpio_triggering(bank, offset, type); in omap_gpio_irq_type()
441 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
444 omap_gpio_init_irq(bank, offset); in omap_gpio_irq_type()
445 if (!omap_gpio_is_input(bank, offset)) { in omap_gpio_irq_type()
446 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
447 retval = -EINVAL; in omap_gpio_irq_type()
450 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
471 void __iomem *reg = bank->base; in omap_clear_gpio_irqbank()
473 reg += bank->regs->irqstatus; in omap_clear_gpio_irqbank()
477 if (bank->regs->irqstatus2) { in omap_clear_gpio_irqbank()
478 reg = bank->base + bank->regs->irqstatus2; in omap_clear_gpio_irqbank()
487 unsigned offset) in omap_clear_gpio_irqstatus() argument
489 omap_clear_gpio_irqbank(bank, BIT(offset)); in omap_clear_gpio_irqstatus()
494 void __iomem *reg = bank->base; in omap_get_gpio_irqbank_mask()
496 u32 mask = (BIT(bank->width)) - 1; in omap_get_gpio_irqbank_mask()
498 reg += bank->regs->irqenable; in omap_get_gpio_irqbank_mask()
500 if (bank->regs->irqenable_inv) in omap_get_gpio_irqbank_mask()
507 unsigned offset, int enable) in omap_set_gpio_irqenable() argument
509 void __iomem *reg = bank->base; in omap_set_gpio_irqenable()
510 u32 gpio_mask = BIT(offset); in omap_set_gpio_irqenable()
512 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { in omap_set_gpio_irqenable()
514 reg += bank->regs->set_irqenable; in omap_set_gpio_irqenable()
515 bank->context.irqenable1 |= gpio_mask; in omap_set_gpio_irqenable()
517 reg += bank->regs->clr_irqenable; in omap_set_gpio_irqenable()
518 bank->context.irqenable1 &= ~gpio_mask; in omap_set_gpio_irqenable()
522 bank->context.irqenable1 = in omap_set_gpio_irqenable()
523 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, in omap_set_gpio_irqenable()
524 enable ^ bank->regs->irqenable_inv); in omap_set_gpio_irqenable()
533 if (bank->regs->wkup_en && in omap_set_gpio_irqenable()
534 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { in omap_set_gpio_irqenable()
535 bank->context.wake_en = in omap_set_gpio_irqenable()
536 omap_gpio_rmw(bank->base + bank->regs->wkup_en, in omap_set_gpio_irqenable()
546 return irq_set_irq_wake(bank->irq, enable); in omap_gpio_wake_enable()
552 * Then we need to mask-read-clear-unmask the triggered GPIO lines
567 isr_reg = bank->base + bank->regs->irqstatus; in omap_gpio_irq_handler()
571 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), in omap_gpio_irq_handler()
576 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
586 edge = isr & ~bank->level_mask; in omap_gpio_irq_handler()
590 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
599 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
607 if (bank->toggle_mask & (BIT(bit))) in omap_gpio_irq_handler()
610 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
612 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); in omap_gpio_irq_handler()
614 generic_handle_domain_irq(bank->chip.irq.domain, bit); in omap_gpio_irq_handler()
616 raw_spin_unlock_irqrestore(&bank->wa_lock, in omap_gpio_irq_handler()
628 unsigned offset = d->hwirq; in omap_gpio_irq_startup() local
630 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_startup()
632 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_startup()
633 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_irq_startup()
634 omap_enable_gpio_module(bank, offset); in omap_gpio_irq_startup()
635 bank->irq_usage |= BIT(offset); in omap_gpio_irq_startup()
637 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_startup()
647 unsigned offset = d->hwirq; in omap_gpio_irq_shutdown() local
649 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_shutdown()
650 bank->irq_usage &= ~(BIT(offset)); in omap_gpio_irq_shutdown()
651 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); in omap_gpio_irq_shutdown()
652 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_irq_shutdown()
653 omap_set_gpio_irqenable(bank, offset, 0); in omap_gpio_irq_shutdown()
654 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_shutdown()
655 omap_clear_gpio_debounce(bank, offset); in omap_gpio_irq_shutdown()
656 omap_disable_gpio_module(bank, offset); in omap_gpio_irq_shutdown()
657 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_shutdown()
664 pm_runtime_get_sync(bank->chip.parent); in omap_gpio_irq_bus_lock()
671 pm_runtime_put(bank->chip.parent); in gpio_irq_bus_sync_unlock()
677 unsigned offset = d->hwirq; in omap_gpio_mask_irq() local
680 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_mask_irq()
681 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); in omap_gpio_mask_irq()
682 omap_set_gpio_irqenable(bank, offset, 0); in omap_gpio_mask_irq()
683 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_mask_irq()
689 unsigned offset = d->hwirq; in omap_gpio_unmask_irq() local
693 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_unmask_irq()
694 omap_set_gpio_irqenable(bank, offset, 1); in omap_gpio_unmask_irq()
697 * For level-triggered GPIOs, clearing must be done after the source in omap_gpio_unmask_irq()
701 if (bank->regs->leveldetect0 && bank->regs->wkup_en && in omap_gpio_unmask_irq()
703 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_unmask_irq()
706 omap_set_gpio_triggering(bank, offset, trigger); in omap_gpio_unmask_irq()
708 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_unmask_irq()
711 /*---------------------------------------------------------------------*/
716 void __iomem *mask_reg = bank->base + in omap_mpuio_suspend_noirq()
717 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_suspend_noirq()
720 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_suspend_noirq()
721 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); in omap_mpuio_suspend_noirq()
722 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_suspend_noirq()
730 void __iomem *mask_reg = bank->base + in omap_mpuio_resume_noirq()
731 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_resume_noirq()
734 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_resume_noirq()
735 writel_relaxed(bank->context.wake_en, mask_reg); in omap_mpuio_resume_noirq()
736 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_resume_noirq()
756 .id = -1,
771 /*---------------------------------------------------------------------*/
773 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) in omap_gpio_request() argument
778 pm_runtime_get_sync(chip->parent); in omap_gpio_request()
780 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_request()
781 omap_enable_gpio_module(bank, offset); in omap_gpio_request()
782 bank->mod_usage |= BIT(offset); in omap_gpio_request()
783 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_request()
788 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) in omap_gpio_free() argument
793 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_free()
794 bank->mod_usage &= ~(BIT(offset)); in omap_gpio_free()
795 if (!LINE_USED(bank->irq_usage, offset)) { in omap_gpio_free()
796 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_free()
797 omap_clear_gpio_debounce(bank, offset); in omap_gpio_free()
799 omap_disable_gpio_module(bank, offset); in omap_gpio_free()
800 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_free()
802 pm_runtime_put(chip->parent); in omap_gpio_free()
805 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) in omap_gpio_get_direction() argument
809 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset)) in omap_gpio_get_direction()
815 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) in omap_gpio_input() argument
821 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_input()
822 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_input()
823 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_input()
827 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) in omap_gpio_get() argument
832 if (omap_gpio_is_input(bank, offset)) in omap_gpio_get()
833 reg = bank->base + bank->regs->datain; in omap_gpio_get()
835 reg = bank->base + bank->regs->dataout; in omap_gpio_get()
837 return (readl_relaxed(reg) & BIT(offset)) != 0; in omap_gpio_get()
840 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) in omap_gpio_output() argument
846 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_output()
847 bank->set_dataout(bank, offset, value); in omap_gpio_output()
848 omap_set_gpio_direction(bank, offset, 0); in omap_gpio_output()
849 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_output()
857 void __iomem *base = bank->base; in omap_gpio_get_multiple()
860 direction = readl_relaxed(base + bank->regs->direction); in omap_gpio_get_multiple()
864 val |= readl_relaxed(base + bank->regs->datain) & m; in omap_gpio_get_multiple()
868 val |= readl_relaxed(base + bank->regs->dataout) & m; in omap_gpio_get_multiple()
875 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, in omap_gpio_debounce() argument
884 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_debounce()
885 ret = omap2_set_gpio_debounce(bank, offset, debounce); in omap_gpio_debounce()
886 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_debounce()
889 dev_info(chip->parent, in omap_gpio_debounce()
891 offset, debounce, ret); in omap_gpio_debounce()
896 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, in omap_gpio_set_config() argument
900 int ret = -ENOTSUPP; in omap_gpio_set_config()
906 ret = gpiochip_generic_config(chip, offset, config); in omap_gpio_set_config()
910 ret = omap_gpio_debounce(chip, offset, debounce); in omap_gpio_set_config()
919 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in omap_gpio_set() argument
925 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set()
926 bank->set_dataout(bank, offset, value); in omap_gpio_set()
927 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set()
934 void __iomem *reg = bank->base + bank->regs->dataout; in omap_gpio_set_multiple()
938 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set_multiple()
941 bank->context.dataout = l; in omap_gpio_set_multiple()
942 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set_multiple()
945 /*---------------------------------------------------------------------*/
952 if (called || bank->regs->revision == USHRT_MAX) in omap_gpio_show_rev()
955 rev = readw_relaxed(bank->base + bank->regs->revision); in omap_gpio_show_rev()
964 void __iomem *base = bank->base; in omap_gpio_mod_init()
967 if (bank->width == 16) in omap_gpio_mod_init()
970 if (bank->is_mpuio) { in omap_gpio_mod_init()
971 writel_relaxed(l, bank->base + bank->regs->irqenable); in omap_gpio_mod_init()
975 omap_gpio_rmw(base + bank->regs->irqenable, l, in omap_gpio_mod_init()
976 bank->regs->irqenable_inv); in omap_gpio_mod_init()
977 omap_gpio_rmw(base + bank->regs->irqstatus, l, in omap_gpio_mod_init()
978 !bank->regs->irqenable_inv); in omap_gpio_mod_init()
979 if (bank->regs->debounce_en) in omap_gpio_mod_init()
980 writel_relaxed(0, base + bank->regs->debounce_en); in omap_gpio_mod_init()
983 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); in omap_gpio_mod_init()
985 if (bank->regs->ctrl) in omap_gpio_mod_init()
986 writel_relaxed(0, base + bank->regs->ctrl); in omap_gpio_mod_init()
998 * REVISIT eventually switch from OMAP-specific gpio structs in omap_gpio_chip_init()
1001 bank->chip.request = omap_gpio_request; in omap_gpio_chip_init()
1002 bank->chip.free = omap_gpio_free; in omap_gpio_chip_init()
1003 bank->chip.get_direction = omap_gpio_get_direction; in omap_gpio_chip_init()
1004 bank->chip.direction_input = omap_gpio_input; in omap_gpio_chip_init()
1005 bank->chip.get = omap_gpio_get; in omap_gpio_chip_init()
1006 bank->chip.get_multiple = omap_gpio_get_multiple; in omap_gpio_chip_init()
1007 bank->chip.direction_output = omap_gpio_output; in omap_gpio_chip_init()
1008 bank->chip.set_config = omap_gpio_set_config; in omap_gpio_chip_init()
1009 bank->chip.set = omap_gpio_set; in omap_gpio_chip_init()
1010 bank->chip.set_multiple = omap_gpio_set_multiple; in omap_gpio_chip_init()
1011 if (bank->is_mpuio) { in omap_gpio_chip_init()
1012 bank->chip.label = "mpuio"; in omap_gpio_chip_init()
1013 if (bank->regs->wkup_en) in omap_gpio_chip_init()
1014 bank->chip.parent = &omap_mpuio_device.dev; in omap_gpio_chip_init()
1015 bank->chip.base = OMAP_MPUIO(0); in omap_gpio_chip_init()
1017 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", in omap_gpio_chip_init()
1018 gpio, gpio + bank->width - 1); in omap_gpio_chip_init()
1020 return -ENOMEM; in omap_gpio_chip_init()
1021 bank->chip.label = label; in omap_gpio_chip_init()
1022 bank->chip.base = gpio; in omap_gpio_chip_init()
1024 bank->chip.ngpio = bank->width; in omap_gpio_chip_init()
1029 * irq_alloc_descs() since a base IRQ offset will no longer be needed. in omap_gpio_chip_init()
1031 irq_base = devm_irq_alloc_descs(bank->chip.parent, in omap_gpio_chip_init()
1032 -1, 0, bank->width, 0); in omap_gpio_chip_init()
1034 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); in omap_gpio_chip_init()
1035 return -ENODEV; in omap_gpio_chip_init()
1040 if (bank->is_mpuio && !bank->regs->wkup_en) in omap_gpio_chip_init()
1041 irqc->irq_set_wake = NULL; in omap_gpio_chip_init()
1043 irq = &bank->chip.irq; in omap_gpio_chip_init()
1044 irq->chip = irqc; in omap_gpio_chip_init()
1045 irq->handler = handle_bad_irq; in omap_gpio_chip_init()
1046 irq->default_type = IRQ_TYPE_NONE; in omap_gpio_chip_init()
1047 irq->num_parents = 1; in omap_gpio_chip_init()
1048 irq->parents = &bank->irq; in omap_gpio_chip_init()
1049 irq->first = irq_base; in omap_gpio_chip_init()
1051 ret = gpiochip_add_data(&bank->chip, bank); in omap_gpio_chip_init()
1053 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n"); in omap_gpio_chip_init()
1055 ret = devm_request_irq(bank->chip.parent, bank->irq, in omap_gpio_chip_init()
1057 0, dev_name(bank->chip.parent), bank); in omap_gpio_chip_init()
1059 gpiochip_remove(&bank->chip); in omap_gpio_chip_init()
1061 if (!bank->is_mpuio) in omap_gpio_chip_init()
1062 gpio += bank->width; in omap_gpio_chip_init()
1069 const struct omap_gpio_reg_offs *regs = p->regs; in omap_gpio_init_context()
1070 void __iomem *base = p->base; in omap_gpio_init_context()
1072 p->context.sysconfig = readl_relaxed(base + regs->sysconfig); in omap_gpio_init_context()
1073 p->context.ctrl = readl_relaxed(base + regs->ctrl); in omap_gpio_init_context()
1074 p->context.oe = readl_relaxed(base + regs->direction); in omap_gpio_init_context()
1075 p->context.wake_en = readl_relaxed(base + regs->wkup_en); in omap_gpio_init_context()
1076 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); in omap_gpio_init_context()
1077 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); in omap_gpio_init_context()
1078 p->context.risingdetect = readl_relaxed(base + regs->risingdetect); in omap_gpio_init_context()
1079 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); in omap_gpio_init_context()
1080 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); in omap_gpio_init_context()
1081 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); in omap_gpio_init_context()
1082 p->context.dataout = readl_relaxed(base + regs->dataout); in omap_gpio_init_context()
1084 p->context_valid = true; in omap_gpio_init_context()
1089 const struct omap_gpio_reg_offs *regs = bank->regs; in omap_gpio_restore_context()
1090 void __iomem *base = bank->base; in omap_gpio_restore_context()
1092 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig); in omap_gpio_restore_context()
1093 writel_relaxed(bank->context.wake_en, base + regs->wkup_en); in omap_gpio_restore_context()
1094 writel_relaxed(bank->context.ctrl, base + regs->ctrl); in omap_gpio_restore_context()
1095 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); in omap_gpio_restore_context()
1096 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); in omap_gpio_restore_context()
1097 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); in omap_gpio_restore_context()
1098 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); in omap_gpio_restore_context()
1099 writel_relaxed(bank->context.dataout, base + regs->dataout); in omap_gpio_restore_context()
1100 writel_relaxed(bank->context.oe, base + regs->direction); in omap_gpio_restore_context()
1102 if (bank->dbck_enable_mask) { in omap_gpio_restore_context()
1103 writel_relaxed(bank->context.debounce, base + regs->debounce); in omap_gpio_restore_context()
1104 writel_relaxed(bank->context.debounce_en, in omap_gpio_restore_context()
1105 base + regs->debounce_en); in omap_gpio_restore_context()
1108 writel_relaxed(bank->context.irqenable1, base + regs->irqenable); in omap_gpio_restore_context()
1109 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); in omap_gpio_restore_context()
1114 struct device *dev = bank->chip.parent; in omap_gpio_idle()
1115 void __iomem *base = bank->base; in omap_gpio_idle()
1118 bank->saved_datain = readl_relaxed(base + bank->regs->datain); in omap_gpio_idle()
1121 if (bank->loses_context) in omap_gpio_idle()
1122 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig); in omap_gpio_idle()
1124 if (!bank->enabled_non_wakeup_gpios) in omap_gpio_idle()
1128 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; in omap_gpio_idle()
1129 mask &= ~bank->context.risingdetect; in omap_gpio_idle()
1130 bank->saved_datain |= mask; in omap_gpio_idle()
1133 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; in omap_gpio_idle()
1134 mask &= ~bank->context.fallingdetect; in omap_gpio_idle()
1135 bank->saved_datain &= ~mask; in omap_gpio_idle()
1142 * non-wakeup GPIOs. Otherwise spurious IRQs will be in omap_gpio_idle()
1145 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { in omap_gpio_idle()
1146 nowake = bank->enabled_non_wakeup_gpios; in omap_gpio_idle()
1147 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); in omap_gpio_idle()
1148 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); in omap_gpio_idle()
1152 if (bank->get_context_loss_count) in omap_gpio_idle()
1153 bank->context_loss_count = in omap_gpio_idle()
1154 bank->get_context_loss_count(dev); in omap_gpio_idle()
1161 struct device *dev = bank->chip.parent; in omap_gpio_unidle()
1170 if (bank->loses_context && !bank->context_valid) { in omap_gpio_unidle()
1173 if (bank->get_context_loss_count) in omap_gpio_unidle()
1174 bank->context_loss_count = in omap_gpio_unidle()
1175 bank->get_context_loss_count(dev); in omap_gpio_unidle()
1180 if (bank->loses_context) { in omap_gpio_unidle()
1181 if (!bank->get_context_loss_count) { in omap_gpio_unidle()
1184 c = bank->get_context_loss_count(dev); in omap_gpio_unidle()
1185 if (c != bank->context_loss_count) { in omap_gpio_unidle()
1193 writel_relaxed(bank->context.fallingdetect, in omap_gpio_unidle()
1194 bank->base + bank->regs->fallingdetect); in omap_gpio_unidle()
1195 writel_relaxed(bank->context.risingdetect, in omap_gpio_unidle()
1196 bank->base + bank->regs->risingdetect); in omap_gpio_unidle()
1199 l = readl_relaxed(bank->base + bank->regs->datain); in omap_gpio_unidle()
1202 * Check if any of the non-wakeup interrupt GPIOs have changed in omap_gpio_unidle()
1207 l ^= bank->saved_datain; in omap_gpio_unidle()
1208 l &= bank->enabled_non_wakeup_gpios; in omap_gpio_unidle()
1214 gen0 = l & bank->context.fallingdetect; in omap_gpio_unidle()
1215 gen0 &= bank->saved_datain; in omap_gpio_unidle()
1217 gen1 = l & bank->context.risingdetect; in omap_gpio_unidle()
1218 gen1 &= ~(bank->saved_datain); in omap_gpio_unidle()
1221 gen = l & (~(bank->context.fallingdetect) & in omap_gpio_unidle()
1222 ~(bank->context.risingdetect)); in omap_gpio_unidle()
1229 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_gpio_unidle()
1230 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_gpio_unidle()
1232 if (!bank->regs->irqstatus_raw0) { in omap_gpio_unidle()
1233 writel_relaxed(old0 | gen, bank->base + in omap_gpio_unidle()
1234 bank->regs->leveldetect0); in omap_gpio_unidle()
1235 writel_relaxed(old1 | gen, bank->base + in omap_gpio_unidle()
1236 bank->regs->leveldetect1); in omap_gpio_unidle()
1239 if (bank->regs->irqstatus_raw0) { in omap_gpio_unidle()
1240 writel_relaxed(old0 | l, bank->base + in omap_gpio_unidle()
1241 bank->regs->leveldetect0); in omap_gpio_unidle()
1242 writel_relaxed(old1 | l, bank->base + in omap_gpio_unidle()
1243 bank->regs->leveldetect1); in omap_gpio_unidle()
1245 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); in omap_gpio_unidle()
1246 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); in omap_gpio_unidle()
1260 raw_spin_lock_irqsave(&bank->lock, flags); in gpio_omap_cpu_notifier()
1261 if (bank->is_suspended) in gpio_omap_cpu_notifier()
1267 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask; in gpio_omap_cpu_notifier()
1281 raw_spin_unlock_irqrestore(&bank->lock, flags); in gpio_omap_cpu_notifier()
1356 .compatible = "ti,omap4-gpio",
1360 .compatible = "ti,omap3-gpio",
1364 .compatible = "ti,omap2-gpio",
1373 struct device *dev = &pdev->dev; in omap_gpio_probe()
1374 struct device_node *node = dev->of_node; in omap_gpio_probe()
1384 return -EINVAL; in omap_gpio_probe()
1388 return -ENOMEM; in omap_gpio_probe()
1392 return -ENOMEM; in omap_gpio_probe()
1394 irqc->irq_startup = omap_gpio_irq_startup, in omap_gpio_probe()
1395 irqc->irq_shutdown = omap_gpio_irq_shutdown, in omap_gpio_probe()
1396 irqc->irq_ack = dummy_irq_chip.irq_ack, in omap_gpio_probe()
1397 irqc->irq_mask = omap_gpio_mask_irq, in omap_gpio_probe()
1398 irqc->irq_unmask = omap_gpio_unmask_irq, in omap_gpio_probe()
1399 irqc->irq_set_type = omap_gpio_irq_type, in omap_gpio_probe()
1400 irqc->irq_set_wake = omap_gpio_wake_enable, in omap_gpio_probe()
1401 irqc->irq_bus_lock = omap_gpio_irq_bus_lock, in omap_gpio_probe()
1402 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, in omap_gpio_probe()
1403 irqc->name = dev_name(&pdev->dev); in omap_gpio_probe()
1404 irqc->flags = IRQCHIP_MASK_ON_SUSPEND; in omap_gpio_probe()
1405 irqc->parent_device = dev; in omap_gpio_probe()
1407 bank->irq = platform_get_irq(pdev, 0); in omap_gpio_probe()
1408 if (bank->irq <= 0) { in omap_gpio_probe()
1409 if (!bank->irq) in omap_gpio_probe()
1410 bank->irq = -ENXIO; in omap_gpio_probe()
1411 return dev_err_probe(dev, bank->irq, "can't get irq resource\n"); in omap_gpio_probe()
1414 bank->chip.parent = dev; in omap_gpio_probe()
1415 bank->chip.owner = THIS_MODULE; in omap_gpio_probe()
1416 bank->dbck_flag = pdata->dbck_flag; in omap_gpio_probe()
1417 bank->stride = pdata->bank_stride; in omap_gpio_probe()
1418 bank->width = pdata->bank_width; in omap_gpio_probe()
1419 bank->is_mpuio = pdata->is_mpuio; in omap_gpio_probe()
1420 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; in omap_gpio_probe()
1421 bank->regs = pdata->regs; in omap_gpio_probe()
1423 bank->chip.of_node = of_node_get(node); in omap_gpio_probe()
1427 if (!of_property_read_bool(node, "ti,gpio-always-on")) in omap_gpio_probe()
1428 bank->loses_context = true; in omap_gpio_probe()
1430 bank->loses_context = pdata->loses_context; in omap_gpio_probe()
1432 if (bank->loses_context) in omap_gpio_probe()
1433 bank->get_context_loss_count = in omap_gpio_probe()
1434 pdata->get_context_loss_count; in omap_gpio_probe()
1437 if (bank->regs->set_dataout && bank->regs->clr_dataout) in omap_gpio_probe()
1438 bank->set_dataout = omap_set_gpio_dataout_reg; in omap_gpio_probe()
1440 bank->set_dataout = omap_set_gpio_dataout_mask; in omap_gpio_probe()
1442 raw_spin_lock_init(&bank->lock); in omap_gpio_probe()
1443 raw_spin_lock_init(&bank->wa_lock); in omap_gpio_probe()
1446 bank->base = devm_platform_ioremap_resource(pdev, 0); in omap_gpio_probe()
1447 if (IS_ERR(bank->base)) { in omap_gpio_probe()
1448 return PTR_ERR(bank->base); in omap_gpio_probe()
1451 if (bank->dbck_flag) { in omap_gpio_probe()
1452 bank->dbck = devm_clk_get(dev, "dbclk"); in omap_gpio_probe()
1453 if (IS_ERR(bank->dbck)) { in omap_gpio_probe()
1456 bank->dbck_flag = false; in omap_gpio_probe()
1458 clk_prepare(bank->dbck); in omap_gpio_probe()
1467 if (bank->is_mpuio) in omap_gpio_probe()
1476 if (bank->dbck_flag) in omap_gpio_probe()
1477 clk_unprepare(bank->dbck); in omap_gpio_probe()
1483 bank->nb.notifier_call = gpio_omap_cpu_notifier; in omap_gpio_probe()
1484 cpu_pm_register_notifier(&bank->nb); in omap_gpio_probe()
1495 cpu_pm_unregister_notifier(&bank->nb); in omap_gpio_remove()
1496 gpiochip_remove(&bank->chip); in omap_gpio_remove()
1497 pm_runtime_disable(&pdev->dev); in omap_gpio_remove()
1498 if (bank->dbck_flag) in omap_gpio_remove()
1499 clk_unprepare(bank->dbck); in omap_gpio_remove()
1509 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_suspend()
1511 bank->is_suspended = true; in omap_gpio_runtime_suspend()
1512 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_suspend()
1522 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_resume()
1524 bank->is_suspended = false; in omap_gpio_runtime_resume()
1525 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_resume()
1534 if (bank->is_suspended) in omap_gpio_suspend()
1537 bank->needs_resume = 1; in omap_gpio_suspend()
1546 if (!bank->needs_resume) in omap_gpio_resume()
1549 bank->needs_resume = 0; in omap_gpio_resume()
1588 MODULE_ALIAS("platform:gpio-omap");