1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
8 #include <linux/gpio/driver.h>
44  * struct mtk - state container for
46  * separate gpio-chip each one with its
51  * @gc_map: array of the gpio chips
69 	struct gpio_chip *gc = &rg->chip;  in mtk_gpio_w32()
72 	offset = (rg->bank * GPIO_BANK_STRIDE) + offset;  in mtk_gpio_w32()
73 	gc->write_reg(mtk->base + offset, val);  in mtk_gpio_w32()
79 	struct gpio_chip *gc = &rg->chip;  in mtk_gpio_r32()
82 	offset = (rg->bank * GPIO_BANK_STRIDE) + offset;  in mtk_gpio_r32()
83 	return gc->read_reg(mtk->base + offset);  in mtk_gpio_r32()
98 		generic_handle_domain_irq(gc->irq.domain, bit);  in mediatek_gpio_irq_handler()
111 	int pin = d->hwirq;  in mediatek_gpio_irq_unmask()
115 	spin_lock_irqsave(&rg->lock, flags);  in mediatek_gpio_irq_unmask()
120 	mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));  in mediatek_gpio_irq_unmask()
121 	mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));  in mediatek_gpio_irq_unmask()
122 	mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));  in mediatek_gpio_irq_unmask()
123 	mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));  in mediatek_gpio_irq_unmask()
124 	spin_unlock_irqrestore(&rg->lock, flags);  in mediatek_gpio_irq_unmask()
132 	int pin = d->hwirq;  in mediatek_gpio_irq_mask()
136 	spin_lock_irqsave(&rg->lock, flags);  in mediatek_gpio_irq_mask()
145 	spin_unlock_irqrestore(&rg->lock, flags);  in mediatek_gpio_irq_mask()
153 	int pin = d->hwirq;  in mediatek_gpio_irq_type()
157 		if ((rg->rising | rg->falling |  in mediatek_gpio_irq_type()
158 		     rg->hlevel | rg->llevel) & mask)  in mediatek_gpio_irq_type()
164 	rg->rising &= ~mask;  in mediatek_gpio_irq_type()
165 	rg->falling &= ~mask;  in mediatek_gpio_irq_type()
166 	rg->hlevel &= ~mask;  in mediatek_gpio_irq_type()
167 	rg->llevel &= ~mask;  in mediatek_gpio_irq_type()
171 		rg->rising |= mask;  in mediatek_gpio_irq_type()
172 		rg->falling |= mask;  in mediatek_gpio_irq_type()
175 		rg->rising |= mask;  in mediatek_gpio_irq_type()
178 		rg->falling |= mask;  in mediatek_gpio_irq_type()
181 		rg->hlevel |= mask;  in mediatek_gpio_irq_type()
184 		rg->llevel |= mask;  in mediatek_gpio_irq_type()
195 	int gpio = spec->args[0];  in mediatek_gpio_xlate()  local
198 	if (rg->bank != gpio / MTK_BANK_WIDTH)  in mediatek_gpio_xlate()
199 		return -EINVAL;  in mediatek_gpio_xlate()
202 		*flags = spec->args[1];  in mediatek_gpio_xlate()
204 	return gpio % MTK_BANK_WIDTH;  in mediatek_gpio_xlate()
216 	rg = &mtk->gc_map[bank];  in mediatek_gpio_bank_probe()
219 	spin_lock_init(&rg->lock);  in mediatek_gpio_bank_probe()
220 	rg->chip.of_node = node;  in mediatek_gpio_bank_probe()
221 	rg->bank = bank;  in mediatek_gpio_bank_probe()
223 	dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);  in mediatek_gpio_bank_probe()
224 	set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);  in mediatek_gpio_bank_probe()
225 	ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);  in mediatek_gpio_bank_probe()
226 	diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);  in mediatek_gpio_bank_probe()
228 	ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,  in mediatek_gpio_bank_probe()
235 	rg->chip.of_gpio_n_cells = 2;  in mediatek_gpio_bank_probe()
236 	rg->chip.of_xlate = mediatek_gpio_xlate;  in mediatek_gpio_bank_probe()
237 	rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",  in mediatek_gpio_bank_probe()
239 	if (!rg->chip.label)  in mediatek_gpio_bank_probe()
240 		return -ENOMEM;  in mediatek_gpio_bank_probe()
242 	rg->chip.offset = bank * MTK_BANK_WIDTH;  in mediatek_gpio_bank_probe()
243 	rg->irq_chip.name = dev_name(dev);  in mediatek_gpio_bank_probe()
244 	rg->irq_chip.parent_device = dev;  in mediatek_gpio_bank_probe()
245 	rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;  in mediatek_gpio_bank_probe()
246 	rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;  in mediatek_gpio_bank_probe()
247 	rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;  in mediatek_gpio_bank_probe()
248 	rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;  in mediatek_gpio_bank_probe()
250 	if (mtk->gpio_irq) {  in mediatek_gpio_bank_probe()
255 		 * a flow-handler because the irq is shared.  in mediatek_gpio_bank_probe()
257 		ret = devm_request_irq(dev, mtk->gpio_irq,  in mediatek_gpio_bank_probe()
259 				       rg->chip.label, &rg->chip);  in mediatek_gpio_bank_probe()
263 				mtk->gpio_irq, ret);  in mediatek_gpio_bank_probe()
267 		girq = &rg->chip.irq;  in mediatek_gpio_bank_probe()
268 		girq->chip = &rg->irq_chip;  in mediatek_gpio_bank_probe()
270 		girq->parent_handler = NULL;  in mediatek_gpio_bank_probe()
271 		girq->num_parents = 0;  in mediatek_gpio_bank_probe()
272 		girq->parents = NULL;  in mediatek_gpio_bank_probe()
273 		girq->default_type = IRQ_TYPE_NONE;  in mediatek_gpio_bank_probe()
274 		girq->handler = handle_simple_irq;  in mediatek_gpio_bank_probe()
277 	ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);  in mediatek_gpio_bank_probe()
279 		dev_err(dev, "Could not register gpio %d, ret=%d\n",  in mediatek_gpio_bank_probe()
280 			rg->chip.ngpio, ret);  in mediatek_gpio_bank_probe()
287 	dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);  in mediatek_gpio_bank_probe()
295 	struct device *dev = &pdev->dev;  in mediatek_gpio_probe()
296 	struct device_node *np = dev->of_node;  in mediatek_gpio_probe()
303 		return -ENOMEM;  in mediatek_gpio_probe()
305 	mtk->base = devm_platform_ioremap_resource(pdev, 0);  in mediatek_gpio_probe()
306 	if (IS_ERR(mtk->base))  in mediatek_gpio_probe()
307 		return PTR_ERR(mtk->base);  in mediatek_gpio_probe()
309 	mtk->gpio_irq = irq_of_parse_and_map(np, 0);  in mediatek_gpio_probe()
310 	mtk->dev = dev;  in mediatek_gpio_probe()
323 	{ .compatible = "mediatek,mt7621-gpio" },