Lines Matching +full:big +full:- +full:endian +full:- +full:regs
43 void __iomem *regs; member
54 * This hardware has a big endian bit assignment such that GPIO line 0 is
60 return BIT(31 - offset); in mpc_pin2mask()
74 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); in mpc8572_gpio_get()
75 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; in mpc8572_gpio_get()
76 out_shadow = gc->bgpio_data & out_mask; in mpc8572_gpio_get()
87 return -EINVAL; in mpc5121_gpio_dir_out()
89 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5121_gpio_dir_out()
98 return -EINVAL; in mpc5125_gpio_dir_out()
100 return mpc8xxx_gc->direction_output(gc, gpio, val); in mpc5125_gpio_dir_out()
107 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) in mpc8xxx_gpio_to_irq()
108 return irq_create_mapping(mpc8xxx_gc->irq, offset); in mpc8xxx_gpio_to_irq()
110 return -ENXIO; in mpc8xxx_gpio_to_irq()
116 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_gpio_irq_cascade()
120 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) in mpc8xxx_gpio_irq_cascade()
121 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); in mpc8xxx_gpio_irq_cascade()
123 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); in mpc8xxx_gpio_irq_cascade()
131 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_unmask()
134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_unmask()
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_unmask()
140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_unmask()
146 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_mask()
149 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
151 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, in mpc8xxx_irq_mask()
152 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) in mpc8xxx_irq_mask()
155 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_mask()
161 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_ack()
163 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, in mpc8xxx_irq_ack()
170 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc8xxx_irq_set_type()
175 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
176 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
177 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
179 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
183 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
184 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, in mpc8xxx_irq_set_type()
185 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) in mpc8xxx_irq_set_type()
187 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc8xxx_irq_set_type()
191 return -EINVAL; in mpc8xxx_irq_set_type()
200 struct gpio_chip *gc = &mpc8xxx_gc->gc; in mpc512x_irq_set_type()
207 reg = mpc8xxx_gc->regs + GPIO_ICR; in mpc512x_irq_set_type()
208 shift = (15 - gpio) * 2; in mpc512x_irq_set_type()
210 reg = mpc8xxx_gc->regs + GPIO_ICR2; in mpc512x_irq_set_type()
211 shift = (15 - (gpio % 16)) * 2; in mpc512x_irq_set_type()
217 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
218 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
220 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
225 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
226 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) in mpc512x_irq_set_type()
228 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
232 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
233 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); in mpc512x_irq_set_type()
234 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); in mpc512x_irq_set_type()
238 return -EINVAL; in mpc512x_irq_set_type()
245 .name = "mpc8xxx-gpio",
256 irq_set_chip_data(irq, h->host_data); in mpc8xxx_gpio_irq_map()
292 { .compatible = "fsl,mpc8349-gpio", },
293 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
294 { .compatible = "fsl,mpc8610-gpio", },
295 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
296 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
297 { .compatible = "fsl,pq3-gpio", },
298 { .compatible = "fsl,ls1028a-gpio", },
299 { .compatible = "fsl,ls1088a-gpio", },
300 { .compatible = "fsl,qoriq-gpio", },
306 struct device_node *np = pdev->dev.of_node; in mpc8xxx_probe()
313 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); in mpc8xxx_probe()
315 return -ENOMEM; in mpc8xxx_probe()
319 raw_spin_lock_init(&mpc8xxx_gc->lock); in mpc8xxx_probe()
321 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); in mpc8xxx_probe()
322 if (IS_ERR(mpc8xxx_gc->regs)) in mpc8xxx_probe()
323 return PTR_ERR(mpc8xxx_gc->regs); in mpc8xxx_probe()
325 gc = &mpc8xxx_gc->gc; in mpc8xxx_probe()
326 gc->parent = &pdev->dev; in mpc8xxx_probe()
328 if (device_property_read_bool(&pdev->dev, "little-endian")) { in mpc8xxx_probe()
329 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
330 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
332 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
336 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); in mpc8xxx_probe()
338 ret = bgpio_init(gc, &pdev->dev, 4, in mpc8xxx_probe()
339 mpc8xxx_gc->regs + GPIO_DAT, in mpc8xxx_probe()
341 mpc8xxx_gc->regs + GPIO_DIR, NULL, in mpc8xxx_probe()
346 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); in mpc8xxx_probe()
349 mpc8xxx_gc->direction_output = gc->direction_output; in mpc8xxx_probe()
351 devtype = device_get_match_data(&pdev->dev); in mpc8xxx_probe()
359 if (devtype->irq_set_type) in mpc8xxx_probe()
360 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; in mpc8xxx_probe()
362 if (devtype->gpio_dir_out) in mpc8xxx_probe()
363 gc->direction_output = devtype->gpio_dir_out; in mpc8xxx_probe()
364 if (devtype->gpio_get) in mpc8xxx_probe()
365 gc->get = devtype->gpio_get; in mpc8xxx_probe()
367 gc->to_irq = mpc8xxx_gpio_to_irq; in mpc8xxx_probe()
376 fwnode = dev_fwnode(&pdev->dev); in mpc8xxx_probe()
377 if (of_device_is_compatible(np, "fsl,qoriq-gpio") || in mpc8xxx_probe()
378 of_device_is_compatible(np, "fsl,ls1028a-gpio") || in mpc8xxx_probe()
379 of_device_is_compatible(np, "fsl,ls1088a-gpio") || in mpc8xxx_probe()
381 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); in mpc8xxx_probe()
383 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc); in mpc8xxx_probe()
385 dev_err(&pdev->dev, in mpc8xxx_probe()
390 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); in mpc8xxx_probe()
391 if (!mpc8xxx_gc->irqn) in mpc8xxx_probe()
394 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, in mpc8xxx_probe()
399 if (!mpc8xxx_gc->irq) in mpc8xxx_probe()
403 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); in mpc8xxx_probe()
404 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); in mpc8xxx_probe()
406 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, in mpc8xxx_probe()
408 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", in mpc8xxx_probe()
411 dev_err(&pdev->dev, in mpc8xxx_probe()
413 mpc8xxx_gc->irqn, ret); in mpc8xxx_probe()
419 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_probe()
427 if (mpc8xxx_gc->irq) { in mpc8xxx_remove()
428 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); in mpc8xxx_remove()
429 irq_domain_remove(mpc8xxx_gc->irq); in mpc8xxx_remove()
447 .name = "gpio-mpc8xxx",