Lines Matching +full:am654 +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DaVinci GPIO Support
5 * Copyright (c) 2006-2007 David Brownell
9 #include <linux/gpio/driver.h>
22 #include <linux/platform_data/gpio-davinci.h>
26 #include <asm-generic/gpio.h>
46 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
60 /* Serialize access to GPIO registers */
67 static inline u32 __gpio_mask(unsigned gpio) in __gpio_mask() argument
69 return 1 << (gpio % 32); in __gpio_mask()
83 /*--------------------------------------------------------------------------*/
85 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
96 g = d->regs[bank]; in __davinci_direction()
97 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
98 temp = readl_relaxed(&g->dir); in __davinci_direction()
101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
105 writel_relaxed(temp, &g->dir); in __davinci_direction()
106 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
126 * Note that changes are synched to the GPIO clock, so reading values back
135 g = d->regs[bank]; in davinci_gpio_get()
137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
141 * Assuming the pin is muxed as a gpio output, set its output value.
150 g = d->regs[bank]; in davinci_gpio_set()
153 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
159 struct device_node *dn = pdev->dev.of_node; in davinci_gpio_get_pdata()
164 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) in davinci_gpio_get_pdata()
165 return dev_get_platdata(&pdev->dev); in davinci_gpio_get_pdata()
167 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in davinci_gpio_get_pdata()
175 pdata->ngpio = val; in davinci_gpio_get_pdata()
177 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); in davinci_gpio_get_pdata()
181 pdata->gpio_unbanked = val; in davinci_gpio_get_pdata()
186 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); in davinci_gpio_get_pdata()
196 struct device *dev = &pdev->dev; in davinci_gpio_probe()
201 return -EINVAL; in davinci_gpio_probe()
204 dev->platform_data = pdata; in davinci_gpio_probe()
207 * The gpio banks conceptually expose a segmented bitmap, in davinci_gpio_probe()
208 * and "ngpio" is one more than the largest zero-based in davinci_gpio_probe()
211 ngpio = pdata->ngpio; in davinci_gpio_probe()
214 return -EINVAL; in davinci_gpio_probe()
225 if (pdata->gpio_unbanked) in davinci_gpio_probe()
226 nirq = pdata->gpio_unbanked; in davinci_gpio_probe()
232 return -ENOMEM; in davinci_gpio_probe()
239 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
240 if (chips->irqs[i] < 0) in davinci_gpio_probe()
241 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); in davinci_gpio_probe()
244 chips->chip.label = dev_name(dev); in davinci_gpio_probe()
246 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
247 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
248 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
249 chips->chip.set = davinci_gpio_set; in davinci_gpio_probe()
251 chips->chip.ngpio = ngpio; in davinci_gpio_probe()
252 chips->chip.base = pdata->no_auto_base ? pdata->base : -1; in davinci_gpio_probe()
255 chips->chip.of_gpio_n_cells = 2; in davinci_gpio_probe()
256 chips->chip.parent = dev; in davinci_gpio_probe()
257 chips->chip.of_node = dev->of_node; in davinci_gpio_probe()
258 chips->chip.request = gpiochip_generic_request; in davinci_gpio_probe()
259 chips->chip.free = gpiochip_generic_free; in davinci_gpio_probe()
261 spin_lock_init(&chips->lock); in davinci_gpio_probe()
265 chips->regs[bank] = gpio_base + offset_array[bank]; in davinci_gpio_probe()
267 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); in davinci_gpio_probe()
279 /*--------------------------------------------------------------------------*/
296 writel_relaxed(mask, &g->clr_falling); in gpio_irq_disable()
297 writel_relaxed(mask, &g->clr_rising); in gpio_irq_disable()
311 writel_relaxed(mask, &g->set_falling); in gpio_irq_enable()
313 writel_relaxed(mask, &g->set_rising); in gpio_irq_enable()
319 return -EINVAL; in gpio_irq_type()
325 .name = "GPIO",
341 bank_num = irqdata->bank_num; in gpio_irq_handler()
342 g = irqdata->regs; in gpio_irq_handler()
343 d = irqdata->chip; in gpio_irq_handler()
357 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
360 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
372 generic_handle_domain_irq(d->irq_domain, hw_irq); in gpio_irq_handler()
376 /* now it may re-trigger */ in gpio_irq_handler()
383 if (d->irq_domain) in gpio_to_irq_banked()
384 return irq_create_mapping(d->irq_domain, offset); in gpio_to_irq_banked()
386 return -ENXIO; in gpio_to_irq_banked()
395 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
397 if (offset < d->gpio_unbanked) in gpio_to_irq_unbanked()
398 return d->irqs[offset]; in gpio_to_irq_unbanked()
400 return -ENODEV; in gpio_to_irq_unbanked()
410 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
412 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
416 return -EINVAL; in gpio_irq_type_unbanked()
421 return -EINVAL; in gpio_irq_type_unbanked()
424 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
426 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
436 (struct davinci_gpio_controller *)d->host_data; in davinci_gpio_irq_map()
437 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map()
482 unsigned gpio, bank; in davinci_gpio_irq_setup() local
488 struct device *dev = &pdev->dev; in davinci_gpio_irq_setup()
490 struct davinci_gpio_platform_data *pdata = dev->platform_data; in davinci_gpio_irq_setup()
505 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; in davinci_gpio_irq_setup()
507 ngpio = pdata->ngpio; in davinci_gpio_irq_setup()
509 clk = devm_clk_get(dev, "gpio"); in davinci_gpio_irq_setup()
511 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); in davinci_gpio_irq_setup()
519 if (!pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
520 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); in davinci_gpio_irq_setup()
527 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, in davinci_gpio_irq_setup()
533 return -ENODEV; in davinci_gpio_irq_setup()
539 * banked IRQs. Having GPIOs in the first GPIO bank use direct in davinci_gpio_irq_setup()
543 chips->chip.to_irq = gpio_to_irq_banked; in davinci_gpio_irq_setup()
544 chips->irq_domain = irq_domain; in davinci_gpio_irq_setup()
547 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO in davinci_gpio_irq_setup()
551 if (pdata->gpio_unbanked) { in davinci_gpio_irq_setup()
552 /* pass "bank 0" GPIO IRQs to AINTC */ in davinci_gpio_irq_setup()
553 chips->chip.to_irq = gpio_to_irq_unbanked; in davinci_gpio_irq_setup()
554 chips->gpio_unbanked = pdata->gpio_unbanked; in davinci_gpio_irq_setup()
555 binten = GENMASK(pdata->gpio_unbanked / 16, 0); in davinci_gpio_irq_setup()
557 /* AINTC handles mask/unmask; GPIO handles triggering */ in davinci_gpio_irq_setup()
558 irq = chips->irqs[0]; in davinci_gpio_irq_setup()
560 irq_chip->name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
561 irq_chip->irq_set_type = gpio_irq_type_unbanked; in davinci_gpio_irq_setup()
564 g = chips->regs[0]; in davinci_gpio_irq_setup()
565 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
566 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
569 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { in davinci_gpio_irq_setup()
570 irq_set_chip(chips->irqs[gpio], irq_chip); in davinci_gpio_irq_setup()
571 irq_set_handler_data(chips->irqs[gpio], chips); in davinci_gpio_irq_setup()
572 irq_set_status_flags(chips->irqs[gpio], in davinci_gpio_irq_setup()
580 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we in davinci_gpio_irq_setup()
583 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { in davinci_gpio_irq_setup()
588 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
589 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
590 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
594 * gpio irqs. Pass the irq bank's corresponding controller to in davinci_gpio_irq_setup()
597 irqdata = devm_kzalloc(&pdev->dev, in davinci_gpio_irq_setup()
603 return -ENOMEM; in davinci_gpio_irq_setup()
606 irqdata->regs = g; in davinci_gpio_irq_setup()
607 irqdata->bank_num = bank; in davinci_gpio_irq_setup()
608 irqdata->chip = chips; in davinci_gpio_irq_setup()
610 irq_set_chained_handler_and_data(chips->irqs[bank], in davinci_gpio_irq_setup()
618 * BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
627 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
628 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
629 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
643 * GPIO driver registration needs to be done before machine_init functions
644 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.