19  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
56 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
57 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
58 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
59 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1    0x3e0f
69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2    0x3e18
70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3    0x3e1f
71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4    0x3e30
72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5    0x3e31
73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6    0x3e32
74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7    0x3e33
75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8    0x3ec2
76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9    0x3ec6
77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10   0x3eca
92 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
93 #define IE31200_MCHBAR_LOW		0x48
94 #define IE31200_MCHBAR_HIGH		0x4c
115  *  0    Single-bit DRAM ECC Error Flag (DSERR)
117 #define IE31200_ERRSTS			0xc8
119 #define IE31200_ERRSTS_CE		BIT(0)
123  * Channel 0 ECC Error Log (64b)
133  *    0  Correctable Error Status (CERRSTS)
136 #define IE31200_C0ECCERRLOG			0x40c8
137 #define IE31200_C1ECCERRLOG			0x44c8
138 #define IE31200_C0ECCERRLOG_SKL			0x4048
139 #define IE31200_C1ECCERRLOG_SKL			0x4448
140 #define IE31200_ECCERRLOG_CE			BIT(0)
151 #define IE31200_CAPID0			0xe4
156 #define IE31200_MAD_DIMM_0_OFFSET		0x5004
157 #define IE31200_MAD_DIMM_0_OFFSET_SKL		0x500C
158 #define IE31200_MAD_DIMM_SIZE			GENMASK_ULL(7, 0)
183 	IE31200 = 0,
205 	   x16_width : 2; /* 0 means x8 width */
217 		edac_dbg(0, "In single channel mode\n");  in how_many_channels()
220 		edac_dbg(0, "In dual channel mode\n");  in how_many_channels()
226 		edac_dbg(0, "2 DIMMS per channel disabled\n");  in how_many_channels()
228 		edac_dbg(0, "2 DIMMS per channel enabled\n");  in how_many_channels()
276 	info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
289 		info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
308 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,  in ie31200_process_error_info()
313 	for (channel = 0; channel < nr_channels; channel++) {  in ie31200_process_error_info()
317 					     0, 0, 0,  in ie31200_process_error_info()
323 					     0, 0,  in ie31200_process_error_info()
356 		ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",  in ie31200_map_mchbar()
363 		ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",  in ie31200_map_mchbar()
373 	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;  in __skl_populate_dimm_info()
382 	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;  in __populate_dimm_info()
383 	dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;  in __populate_dimm_info()
412 	edac_dbg(0, "MC:\n");  in ie31200_probe1()
420 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;  in ie31200_probe1()
421 	layers[0].size = IE31200_DIMMS;  in ie31200_probe1()
422 	layers[0].is_virt_csrow = true;  in ie31200_probe1()
426 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,  in ie31200_probe1()
463 	for (i = 0; i < IE31200_CHANNELS; i++) {  in ie31200_probe1()
466 		edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);  in ie31200_probe1()
467 		for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {  in ie31200_probe1()
470 			edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",  in ie31200_probe1()
483 	for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {  in ie31200_probe1()
484 		for (j = 0; j < IE31200_CHANNELS; j++) {  in ie31200_probe1()
489 			if (nr_pages == 0)  in ie31200_probe1()
494 				dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);  in ie31200_probe1()
496 				edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);  in ie31200_probe1()
505 			dimm = edac_get_dimm(mci, i * 2, j, 0);  in ie31200_probe1()
507 			edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);  in ie31200_probe1()
528 	return 0;  in ie31200_probe1()
544 	edac_dbg(0, "MC:\n");  in ie31200_init_one()
545 	if (pci_enable_device(pdev) < 0)  in ie31200_init_one()
548 	if (rc == 0 && !mci_pdev)  in ie31200_init_one()
559 	edac_dbg(0, "\n");  in ie31200_remove_one()
571 	{ PCI_VEND_DEV(INTEL, IE31200_HB_1),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
572 	{ PCI_VEND_DEV(INTEL, IE31200_HB_2),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
573 	{ PCI_VEND_DEV(INTEL, IE31200_HB_3),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
574 	{ PCI_VEND_DEV(INTEL, IE31200_HB_4),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
575 	{ PCI_VEND_DEV(INTEL, IE31200_HB_5),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
576 	{ PCI_VEND_DEV(INTEL, IE31200_HB_6),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
577 	{ PCI_VEND_DEV(INTEL, IE31200_HB_7),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
578 	{ PCI_VEND_DEV(INTEL, IE31200_HB_8),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
579 	{ PCI_VEND_DEV(INTEL, IE31200_HB_9),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
580 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
581 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
582 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
583 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
584 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
585 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
586 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
587 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
588 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
589 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
590 	{ 0, } /* 0 terminated list. */
610 	if (pci_rc < 0)  in ie31200_init()
614 		ie31200_registered = 0;  in ie31200_init()
615 		for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {  in ie31200_init()
623 			edac_dbg(0, "ie31200 pci_get_device fail\n");  in ie31200_init()
628 		if (pci_rc < 0) {  in ie31200_init()
629 			edac_dbg(0, "ie31200 init fail\n");  in ie31200_init()
634 	return 0;  in ie31200_init()