Lines Matching refs:dclr
1032 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
1034 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); in debug_dump_dramcfg_low()
1047 (dclr & BIT(19)) ? "yes" : "no"); in debug_dump_dramcfg_low()
1051 (dclr & BIT(8)) ? "enabled" : "disabled"); in debug_dump_dramcfg_low()
1055 (dclr & BIT(11)) ? "128b" : "64b"); in debug_dump_dramcfg_low()
1058 (dclr & BIT(12)) ? "yes" : "no", in debug_dump_dramcfg_low()
1059 (dclr & BIT(13)) ? "yes" : "no", in debug_dump_dramcfg_low()
1060 (dclr & BIT(14)) ? "yes" : "no", in debug_dump_dramcfg_low()
1061 (dclr & BIT(15)) ? "yes" : "no"); in debug_dump_dramcfg_low()
1622 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select() local
1626 return ddr2_cs_size(cs_mode, dclr & WIDTH_128); in k8_dbam_to_chip_select()
1789 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select() local
1794 return ddr3_cs_size(cs_mode, dclr & WIDTH_128); in f10_dbam_to_chip_select()
1796 return ddr2_cs_size(cs_mode, dclr & WIDTH_128); in f10_dbam_to_chip_select()