Lines Matching +full:use +full:- +full:minimum +full:- +full:ecc
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Set by command line parameter. If BIOS has enabled the ECC, this override is
9 * cleared to prevent re-enabling the hardware by this driver.
18 /* Per-node stuff */
26 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
68 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
81 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
93 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
94 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
96 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
106 * DCT0 -> F2x040..
107 * DCT1 -> F2x140..
116 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
119 return -EINVAL; in amd64_read_dct_pci_cfg()
141 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
147 return -EINVAL; in amd64_read_dct_pci_cfg()
153 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
163 * (dram) over to cache lines. This is nasty, so we will use bandwidth in
178 scrubval -= 0x5; in __f17h_set_scrubval()
179 pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF); in __f17h_set_scrubval()
180 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1); in __f17h_set_scrubval()
182 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1); in __f17h_set_scrubval()
187 * issue. If requested is too big, then use last maximum value found.
203 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { in __set_scrub_rate()
217 if (pvt->umc) { in __set_scrub_rate()
219 } else if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
221 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
223 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
225 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
236 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate()
239 if (pvt->fam == 0xf) in set_scrub_rate()
242 if (pvt->fam == 0x15) { in set_scrub_rate()
244 if (pvt->model < 0x10) in set_scrub_rate()
247 if (pvt->model == 0x60) in set_scrub_rate()
255 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate()
256 int i, retval = -EINVAL; in get_scrub_rate()
259 if (pvt->umc) { in get_scrub_rate()
260 amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); in get_scrub_rate()
262 amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); in get_scrub_rate()
268 } else if (pvt->fam == 0x15) { in get_scrub_rate()
270 if (pvt->model < 0x10) in get_scrub_rate()
273 if (pvt->model == 0x60) in get_scrub_rate()
274 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
276 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
278 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
300 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be in base_limit_match()
302 * Here we discard bits 63-40. See section 3.4.2 of AMD publication in base_limit_match()
303 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 in base_limit_match()
326 * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section in find_mc_by_sys_addr()
329 pvt = mci->pvt_info; in find_mc_by_sys_addr()
391 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
392 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
393 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
402 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
403 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
404 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
405 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
420 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
421 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
424 if (pvt->fam == 0x15) in get_cs_base_and_mask()
442 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
445 pvt->csels[dct].csbases[i]
448 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
451 for (i = 0; i < fam_type->max_mcs; i++)
455 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
463 pvt = mci->pvt_info; in input_addr_to_csrow()
476 pvt->mc_node_id); in input_addr_to_csrow()
482 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
484 return -1; in input_addr_to_csrow()
493 * - The revision of the node is not E or greater. In this case, the DRAM Hole
496 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
500 * complete 32-bit values despite the fact that the bitfields in the DHAR
501 * only represent bits 31-24 of the base and offset values.
506 struct amd64_pvt *pvt = mci->pvt_info; in get_dram_hole_info()
509 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in get_dram_hole_info()
511 pvt->ext_model, pvt->mc_node_id); in get_dram_hole_info()
516 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in get_dram_hole_info()
523 pvt->mc_node_id); in get_dram_hole_info()
529 /* +------------------+--------------------+--------------------+----- in get_dram_hole_info()
531 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | in get_dram_hole_info()
535 * | | | (0xffffffff-x))] | in get_dram_hole_info()
536 * +------------------+--------------------+--------------------+----- in get_dram_hole_info()
546 *hole_size = (1ULL << 32) - *hole_base; in get_dram_hole_info()
548 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in get_dram_hole_info()
552 pvt->mc_node_id, (unsigned long)*hole_base, in get_dram_hole_info()
564 struct amd64_pvt *pvt = mci->pvt_info; \
566 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
615 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_show()
616 return sprintf(buf, "0x%x\n", pvt->injection.section); in inject_section_show()
620 * store error injection section value which refers to one of 4 16-byte sections
621 * within a 64-byte cacheline
630 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_store()
640 return -EINVAL; in inject_section_store()
643 pvt->injection.section = (u32) value; in inject_section_store()
651 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_show()
652 return sprintf(buf, "0x%x\n", pvt->injection.word); in inject_word_show()
656 * store error injection word value which refers to one of 9 16-bit word of the
657 * 16-byte (128-bit + ECC bits) section
666 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_store()
676 return -EINVAL; in inject_word_store()
679 pvt->injection.word = (u32) value; in inject_word_store()
688 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_show()
689 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in inject_ecc_vector_show()
695 * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
702 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_store()
712 return -EINVAL; in inject_ecc_vector_store()
715 pvt->injection.bit_map = (u32) value; in inject_ecc_vector_store()
720 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
728 struct amd64_pvt *pvt = mci->pvt_info; in inject_read_store()
737 /* Form value to choose 16-byte section of cacheline */ in inject_read_store()
738 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_read_store()
740 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_read_store()
742 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); in inject_read_store()
745 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_read_store()
753 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
761 struct amd64_pvt *pvt = mci->pvt_info; in inject_write_store()
770 /* Form value to choose 16-byte section of cacheline */ in inject_write_store()
771 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_write_store()
773 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_write_store()
775 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); in inject_write_store()
784 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_write_store()
788 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); in inject_write_store()
824 struct amd64_pvt *pvt = mci->pvt_info; in inj_is_visible()
827 if (pvt->fam >= 0x10 && pvt->fam <= 0x16) in inj_is_visible()
828 return attr->mode; in inj_is_visible()
870 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr()
874 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
880 /* use DHAR to translate SysAddr to DramAddr */ in sys_addr_to_dram_addr()
881 dram_addr = sys_addr - hole_offset; in sys_addr_to_dram_addr()
893 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 in sys_addr_to_dram_addr()
894 * only deals with 40-bit values. Therefore we discard bits 63-40 of in sys_addr_to_dram_addr()
897 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture in sys_addr_to_dram_addr()
900 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; in sys_addr_to_dram_addr()
929 pvt = mci->pvt_info; in dram_addr_to_input_addr()
932 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) in dram_addr_to_input_addr()
967 err->page = (u32) (error_address >> PAGE_SHIFT); in error_address_to_page_and_offset()
968 err->offset = ((u32) error_address) & ~PAGE_MASK; in error_address_to_page_and_offset()
974 * of a node that detected an ECC memory error. mci represents the node that
976 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
985 if (csrow == -1) in sys_addr_to_csrow()
994 * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
995 * are ECC capable.
1002 if (pvt->umc) { in determine_edac_cap()
1006 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in determine_edac_cap()
1012 if (pvt->umc[i].umc_cfg & BIT(12)) in determine_edac_cap()
1019 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in determine_edac_cap()
1023 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()
1036 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1037 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
1040 * same 'type' until proven otherwise. So, use a cs in debug_dump_dramcfg_low()
1046 edac_dbg(1, "All DIMMs support ECC:%s\n", in debug_dump_dramcfg_low()
1053 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
1082 /* Asymmetric dual-rank DIMM support. */ in f17_get_cs_mode()
1101 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); in debug_display_dimm_sizes_df()
1102 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); in debug_display_dimm_sizes_df()
1117 umc = &pvt->umc[i]; in __dump_misc_regs_df()
1119 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in __dump_misc_regs_df()
1120 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in __dump_misc_regs_df()
1121 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in __dump_misc_regs_df()
1122 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in __dump_misc_regs_df()
1124 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); in __dump_misc_regs_df()
1125 edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp); in __dump_misc_regs_df()
1127 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); in __dump_misc_regs_df()
1129 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); in __dump_misc_regs_df()
1131 edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n", in __dump_misc_regs_df()
1132 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", in __dump_misc_regs_df()
1133 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); in __dump_misc_regs_df()
1134 edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n", in __dump_misc_regs_df()
1135 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); in __dump_misc_regs_df()
1137 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); in __dump_misc_regs_df()
1139 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); in __dump_misc_regs_df()
1141 if (pvt->dram_type == MEM_LRDDR4) { in __dump_misc_regs_df()
1142 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); in __dump_misc_regs_df()
1151 pvt->dhar, dhar_base(pvt)); in __dump_misc_regs_df()
1157 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in __dump_misc_regs()
1160 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in __dump_misc_regs()
1162 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n", in __dump_misc_regs()
1163 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in __dump_misc_regs()
1164 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in __dump_misc_regs()
1166 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in __dump_misc_regs()
1168 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in __dump_misc_regs()
1171 pvt->dhar, dhar_base(pvt), in __dump_misc_regs()
1172 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in __dump_misc_regs()
1178 if (pvt->fam == 0xf) in __dump_misc_regs()
1185 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in __dump_misc_regs()
1191 if (pvt->umc) in dump_misc_regs()
1198 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dump_misc_regs()
1206 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in prep_chip_selects()
1207 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
1208 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in prep_chip_selects()
1209 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in prep_chip_selects()
1210 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in prep_chip_selects()
1211 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in prep_chip_selects()
1212 } else if (pvt->fam >= 0x17) { in prep_chip_selects()
1216 pvt->csels[umc].b_cnt = 4; in prep_chip_selects()
1217 pvt->csels[umc].m_cnt = 2; in prep_chip_selects()
1221 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
1222 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in prep_chip_selects()
1241 base = &pvt->csels[umc].csbases[cs]; in read_umc_base_mask()
1242 base_sec = &pvt->csels[umc].csbases_sec[cs]; in read_umc_base_mask()
1247 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) in read_umc_base_mask()
1251 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) in read_umc_base_mask()
1260 mask = &pvt->csels[umc].csmasks[cs]; in read_umc_base_mask()
1261 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in read_umc_base_mask()
1266 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) in read_umc_base_mask()
1270 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) in read_umc_base_mask()
1286 if (pvt->umc) in read_dct_base_mask()
1292 u32 *base0 = &pvt->csels[0].csbases[cs]; in read_dct_base_mask()
1293 u32 *base1 = &pvt->csels[1].csbases[cs]; in read_dct_base_mask()
1299 if (pvt->fam == 0xf) in read_dct_base_mask()
1304 cs, *base1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1311 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in read_dct_base_mask()
1312 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask()
1318 if (pvt->fam == 0xf) in read_dct_base_mask()
1323 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1332 if (pvt->umc) { in determine_memory_type()
1333 if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) in determine_memory_type()
1334 pvt->dram_type = MEM_LRDDR4; in determine_memory_type()
1335 else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) in determine_memory_type()
1336 pvt->dram_type = MEM_RDDR4; in determine_memory_type()
1338 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1342 switch (pvt->fam) { in determine_memory_type()
1344 if (pvt->ext_model >= K8_REV_F) in determine_memory_type()
1347 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()
1351 if (pvt->dchr0 & DDR3_MODE) in determine_memory_type()
1354 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()
1358 if (pvt->model < 0x60) in determine_memory_type()
1364 * We use a Chip Select value of '0' to obtain dcsm. in determine_memory_type()
1371 dcsm = pvt->csels[0].csmasks[0]; in determine_memory_type()
1374 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1375 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()
1376 pvt->dram_type = MEM_DDR3; in determine_memory_type()
1378 pvt->dram_type = MEM_LRDDR3; in determine_memory_type()
1380 pvt->dram_type = MEM_RDDR3; in determine_memory_type()
1388 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in determine_memory_type()
1389 pvt->dram_type = MEM_EMPTY; in determine_memory_type()
1394 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()
1402 if (pvt->ext_model >= K8_REV_F) in k8_early_channel_count()
1404 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()
1407 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()
1410 pvt->dclr1 = 0; in k8_early_channel_count()
1418 u16 mce_nid = topology_die_id(m->extcpu); in get_error_address()
1428 pvt = mci->pvt_info; in get_error_address()
1430 if (pvt->fam == 0xf) { in get_error_address()
1435 addr = m->addr & GENMASK_ULL(end_bit, start_bit); in get_error_address()
1440 if (pvt->fam == 0x15) { in get_error_address()
1449 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1464 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1488 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) && in pci_get_related_function()
1489 (dev->bus->number == related->bus->number) && in pci_get_related_function()
1490 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) in pci_get_related_function()
1505 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1506 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1508 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1514 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1515 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1518 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1525 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1527 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1532 f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc); in read_dram_base_limit_regs()
1538 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1541 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1543 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1546 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1554 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow()
1562 err->src_mci = find_mc_by_sys_addr(mci, sys_addr); in k8_map_sysaddr_to_csrow()
1563 if (!err->src_mci) { in k8_map_sysaddr_to_csrow()
1566 err->err_code = ERR_NODE; in k8_map_sysaddr_to_csrow()
1571 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); in k8_map_sysaddr_to_csrow()
1572 if (err->csrow < 0) { in k8_map_sysaddr_to_csrow()
1573 err->err_code = ERR_CSROW; in k8_map_sysaddr_to_csrow()
1578 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1579 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in k8_map_sysaddr_to_csrow()
1580 if (err->channel < 0) { in k8_map_sysaddr_to_csrow()
1586 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " in k8_map_sysaddr_to_csrow()
1588 err->syndrome); in k8_map_sysaddr_to_csrow()
1589 err->err_code = ERR_CHANNEL; in k8_map_sysaddr_to_csrow()
1594 * non-chipkill ecc mode in k8_map_sysaddr_to_csrow()
1597 * channel number when using non-chipkill memory. This method in k8_map_sysaddr_to_csrow()
1599 * (Wish the email was placed in this comment - norsk) in k8_map_sysaddr_to_csrow()
1601 err->channel = ((sys_addr & BIT(3)) != 0); in k8_map_sysaddr_to_csrow()
1622 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1624 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1628 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1658 return 32 << (cs_mode - diff); in k8_dbam_to_chip_select()
1667 * Get the number of DCT channels in use.
1679 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()
1690 edac_dbg(0, "Data width is not 128 bits - need more decoding\n"); in f1x_early_channel_count()
1698 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); in f1x_early_channel_count()
1722 channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); in f17_early_channel_count()
1735 cs_size = -1; in ddr3_cs_size()
1745 if (cs_size != -1) in ddr3_cs_size()
1757 cs_size = -1; in ddr3_lrdimm_cs_size()
1765 if (cs_size != -1) in ddr3_lrdimm_cs_size()
1776 cs_size = -1; in ddr4_cs_size()
1789 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1793 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1815 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1819 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1821 return -1; in f15_m60h_dbam_to_chip_select()
1824 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1831 /* Minimum cs size is 512mb for F15hM60h*/ in f15_m60h_dbam_to_chip_select()
1833 return -1; in f15_m60h_dbam_to_chip_select()
1851 return -1; in f16_dbam_to_chip_select()
1877 * CS0 and CS1 -> DIMM0 in f17_addr_mask_to_cs_size()
1878 * CS2 and CS3 -> DIMM1 in f17_addr_mask_to_cs_size()
1882 /* Asymmetric dual-rank DIMM support. */ in f17_addr_mask_to_cs_size()
1884 addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm]; in f17_addr_mask_to_cs_size()
1886 addr_mask_orig = pvt->csels[umc].csmasks[dimm]; in f17_addr_mask_to_cs_size()
1895 msb = fls(addr_mask_orig) - 1; in f17_addr_mask_to_cs_size()
1897 num_zero_bits = msb - weight; in f17_addr_mask_to_cs_size()
1900 addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); in f17_addr_mask_to_cs_size()
1916 if (pvt->fam == 0xf) in read_dram_ctl_register()
1919 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
1921 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
1930 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n", in read_dram_ctl_register()
1940 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
1981 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
1990 * see F2x110[DctSelIntLvAddr] - channel interleave mode in f1x_determine_channel()
2029 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
2066 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); in f1x_get_norm_dct_addr()
2095 * -EINVAL: NOT FOUND
2096 * 0..csrow = Chip-Select Row
2103 int cs_found = -EINVAL; in f1x_lookup_addr_in_dct()
2110 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
2129 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
2143 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
2144 * swapped with a region located at the bottom of memory so that the GPU can use
2151 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
2153 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
2157 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
2180 int cs_found = -EINVAL; in f1x_match_to_this_node()
2198 return -EINVAL; in f1x_match_to_this_node()
2202 return -EINVAL; in f1x_match_to_this_node()
2260 int cs_found = -EINVAL; in f15_m30h_match_to_this_node()
2272 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2273 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2283 return -EINVAL; in f15_m30h_match_to_this_node()
2290 return -EINVAL; in f15_m30h_match_to_this_node()
2300 return -EINVAL; in f15_m30h_match_to_this_node()
2306 return -EINVAL; in f15_m30h_match_to_this_node()
2308 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2316 return -EINVAL; in f15_m30h_match_to_this_node()
2326 chan_addr = sys_addr - chan_offset; in f15_m30h_match_to_this_node()
2337 return -EINVAL; in f15_m30h_match_to_this_node()
2347 return -EINVAL; in f15_m30h_match_to_this_node()
2351 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2366 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2383 int cs_found = -EINVAL; in f1x_translate_sysaddr_to_cs()
2390 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2416 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow()
2420 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2421 if (err->csrow < 0) { in f1x_map_sysaddr_to_csrow()
2422 err->err_code = ERR_CSROW; in f1x_map_sysaddr_to_csrow()
2432 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in f1x_map_sysaddr_to_csrow()
2442 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in debug_display_dimm_sizes()
2443 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in debug_display_dimm_sizes()
2445 if (pvt->fam == 0xf) { in debug_display_dimm_sizes()
2447 if (pvt->ext_model < K8_REV_F) in debug_display_dimm_sizes()
2453 if (pvt->fam == 0x10) { in debug_display_dimm_sizes()
2454 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in debug_display_dimm_sizes()
2455 : pvt->dbam0; in debug_display_dimm_sizes()
2457 pvt->csels[1].csbases : in debug_display_dimm_sizes()
2458 pvt->csels[0].csbases; in debug_display_dimm_sizes()
2460 dbam = pvt->dbam0; in debug_display_dimm_sizes()
2461 dcsb = pvt->csels[1].csbases; in debug_display_dimm_sizes()
2479 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2485 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2736 return -1; in decode_syndrome()
2759 return -1; in map_err_sym_to_channel()
2767 return -1; in map_err_sym_to_channel()
2772 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome()
2773 int err_sym = -1; in get_channel_from_ecc_syndrome()
2775 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2778 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2779 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2782 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2784 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2788 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2808 switch (err->err_code) { in __log_ecc_error()
2819 string = "Unknown syndrome - possible error reporting race"; in __log_ecc_error()
2822 string = "MCA_SYND not valid - unknown syndrome and csrow"; in __log_ecc_error()
2833 err->page, err->offset, err->syndrome, in __log_ecc_error()
2834 err->csrow, err->channel, -1, in __log_ecc_error()
2842 u8 ecc_type = (m->status >> 45) & 0x3; in decode_bus_error()
2843 u8 xec = XEC(m->status, 0x1f); in decode_bus_error()
2844 u16 ec = EC(m->status); in decode_bus_error()
2852 pvt = mci->pvt_info; in decode_bus_error()
2858 /* Do only ECC errors */ in decode_bus_error()
2867 err.syndrome = extract_syndrome(m->status); in decode_bus_error()
2869 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2885 return (m->ipid & GENMASK(31, 0)) >> 20; in find_umc_channel()
2890 u8 ecc_type = (m->status >> 45) & 0x3; in decode_umc_error()
2900 pvt = mci->pvt_info; in decode_umc_error()
2904 if (m->status & MCI_STATUS_DEFERRED) in decode_umc_error()
2909 if (!(m->status & MCI_STATUS_SYNDV)) { in decode_umc_error()
2915 u8 length = (m->synd >> 18) & 0x3f; in decode_umc_error()
2918 err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0); in decode_umc_error()
2923 err.csrow = m->synd & 0x7; in decode_umc_error()
2925 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { in decode_umc_error()
2937 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2944 if (pvt->umc) { in reserve_mc_sibling_devs()
2945 pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2946 if (!pvt->F0) { in reserve_mc_sibling_devs()
2948 return -ENODEV; in reserve_mc_sibling_devs()
2951 pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2952 if (!pvt->F6) { in reserve_mc_sibling_devs()
2953 pci_dev_put(pvt->F0); in reserve_mc_sibling_devs()
2954 pvt->F0 = NULL; in reserve_mc_sibling_devs()
2957 return -ENODEV; in reserve_mc_sibling_devs()
2961 pci_ctl_dev = &pvt->F0->dev; in reserve_mc_sibling_devs()
2963 edac_dbg(1, "F0: %s\n", pci_name(pvt->F0)); in reserve_mc_sibling_devs()
2964 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2965 edac_dbg(1, "F6: %s\n", pci_name(pvt->F6)); in reserve_mc_sibling_devs()
2971 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2972 if (!pvt->F1) { in reserve_mc_sibling_devs()
2974 return -ENODEV; in reserve_mc_sibling_devs()
2978 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2979 if (!pvt->F2) { in reserve_mc_sibling_devs()
2980 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2981 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2984 return -ENODEV; in reserve_mc_sibling_devs()
2988 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2990 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2991 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2992 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2999 if (pvt->umc) { in free_mc_sibling_devs()
3000 pci_dev_put(pvt->F0); in free_mc_sibling_devs()
3001 pci_dev_put(pvt->F6); in free_mc_sibling_devs()
3003 pci_dev_put(pvt->F1); in free_mc_sibling_devs()
3004 pci_dev_put(pvt->F2); in free_mc_sibling_devs()
3010 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
3012 if (pvt->umc) { in determine_ecc_sym_sz()
3017 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in determine_ecc_sym_sz()
3018 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
3019 pvt->ecc_sym_sz = 16; in determine_ecc_sym_sz()
3021 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
3022 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
3027 } else if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
3030 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
3032 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
3033 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
3035 /* F10h, revD and later can do x8 ECC too. */ in determine_ecc_sym_sz()
3036 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
3037 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
3046 u8 nid = pvt->mc_node_id; in __read_mc_regs_df()
3054 umc = &pvt->umc[i]; in __read_mc_regs_df()
3056 amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg); in __read_mc_regs_df()
3057 amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); in __read_mc_regs_df()
3058 amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); in __read_mc_regs_df()
3059 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in __read_mc_regs_df()
3060 amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); in __read_mc_regs_df()
3075 * those are Read-As-Zero. in read_mc_regs()
3077 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in read_mc_regs()
3078 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in read_mc_regs()
3083 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in read_mc_regs()
3084 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in read_mc_regs()
3089 if (pvt->umc) { in read_mc_regs()
3091 amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); in read_mc_regs()
3096 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in read_mc_regs()
3117 (rw & 0x1) ? "R" : "-", in read_mc_regs()
3118 (rw & 0x2) ? "W" : "-", in read_mc_regs()
3123 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in read_mc_regs()
3124 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in read_mc_regs()
3126 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in read_mc_regs()
3128 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in read_mc_regs()
3129 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in read_mc_regs()
3132 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in read_mc_regs()
3133 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in read_mc_regs()
3140 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in read_mc_regs()
3149 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
3150 * k8 private pointer to -->
3158 * 0-3 CSROWs 0 and 1
3159 * 4-7 CSROWs 2 and 3
3160 * 8-11 CSROWs 4 and 5
3161 * 12-15 CSROWs 6 and 7
3164 * The meaning of the values depends on CPU revision and dual-channel state,
3181 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in get_csrow_nr_pages()
3185 if (!pvt->umc) { in get_csrow_nr_pages()
3192 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in get_csrow_nr_pages()
3193 nr_pages <<= 20 - PAGE_SHIFT; in get_csrow_nr_pages()
3204 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows_df()
3211 if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) { in init_csrows_df()
3214 } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) { in init_csrows_df()
3217 } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) { in init_csrows_df()
3220 } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) { in init_csrows_df()
3230 dimm = mci->csrows[cs]->channels[umc]->dimm; in init_csrows_df()
3233 pvt->mc_node_id, cs); in init_csrows_df()
3235 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); in init_csrows_df()
3236 dimm->mtype = pvt->dram_type; in init_csrows_df()
3237 dimm->edac_mode = edac_mode; in init_csrows_df()
3238 dimm->dtype = dev_type; in init_csrows_df()
3239 dimm->grain = 64; in init_csrows_df()
3252 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows()
3260 if (pvt->umc) in init_csrows()
3263 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in init_csrows()
3265 pvt->nbcfg = val; in init_csrows()
3268 pvt->mc_node_id, val, in init_csrows()
3278 if (pvt->fam != 0xf) in init_csrows()
3284 csrow = mci->csrows[i]; in init_csrows()
3288 pvt->mc_node_id, i); in init_csrows()
3292 csrow->channels[0]->dimm->nr_pages = nr_pages; in init_csrows()
3296 if (pvt->fam != 0xf && row_dct1) { in init_csrows()
3299 csrow->channels[1]->dimm->nr_pages = row_dct1_pages; in init_csrows()
3305 /* Determine DIMM ECC mode: */ in init_csrows()
3306 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in init_csrows()
3307 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in init_csrows()
3312 for (j = 0; j < pvt->channel_count; j++) { in init_csrows()
3313 dimm = csrow->channels[j]->dimm; in init_csrows()
3314 dimm->mtype = pvt->dram_type; in init_csrows()
3315 dimm->edac_mode = edac_mode; in init_csrows()
3316 dimm->grain = 64; in init_csrows()
3351 nbe = reg->l & MSR_MCGCTL_NBE; in nb_mce_bank_enabled_on_node()
3354 cpu, reg->q, in nb_mce_bank_enabled_on_node()
3374 return -ENOMEM; in toggle_ecc_err_reporting()
3386 if (reg->l & MSR_MCGCTL_NBE) in toggle_ecc_err_reporting()
3387 s->flags.nb_mce_enable = 1; in toggle_ecc_err_reporting()
3389 reg->l |= MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3394 if (!s->flags.nb_mce_enable) in toggle_ecc_err_reporting()
3395 reg->l &= ~MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3412 amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); in enable_ecc_error_reporting()
3418 s->old_nbctl = value & mask; in enable_ecc_error_reporting()
3419 s->nbctl_valid = true; in enable_ecc_error_reporting()
3430 amd64_warn("DRAM ECC disabled on this node, enabling...\n"); in enable_ecc_error_reporting()
3432 s->flags.nb_ecc_prev = 0; in enable_ecc_error_reporting()
3434 /* Attempt to turn on DRAM ECC Enable */ in enable_ecc_error_reporting()
3441 amd64_warn("Hardware rejected DRAM ECC enable," in enable_ecc_error_reporting()
3445 amd64_info("Hardware accepted DRAM ECC Enable\n"); in enable_ecc_error_reporting()
3448 s->flags.nb_ecc_prev = 1; in enable_ecc_error_reporting()
3462 if (!s->nbctl_valid) in restore_ecc_error_reporting()
3467 value |= s->old_nbctl; in restore_ecc_error_reporting()
3471 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ in restore_ecc_error_reporting()
3472 if (!s->flags.nb_ecc_prev) { in restore_ecc_error_reporting()
3485 u16 nid = pvt->mc_node_id; in ecc_enabled()
3495 umc = &pvt->umc[i]; in ecc_enabled()
3498 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) in ecc_enabled()
3503 if (umc->umc_cap_hi & UMC_ECC_ENABLED) in ecc_enabled()
3516 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in ecc_enabled()
3526 edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled")); in ecc_enabled()
3540 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in f17h_determine_edac_ctl_cap()
3541 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in f17h_determine_edac_ctl_cap()
3542 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in f17h_determine_edac_ctl_cap()
3544 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in f17h_determine_edac_ctl_cap()
3545 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in f17h_determine_edac_ctl_cap()
3549 /* Set chipkill only if ECC is enabled: */ in f17h_determine_edac_ctl_cap()
3551 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in f17h_determine_edac_ctl_cap()
3557 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in f17h_determine_edac_ctl_cap()
3559 mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED; in f17h_determine_edac_ctl_cap()
3561 mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED; in f17h_determine_edac_ctl_cap()
3567 struct amd64_pvt *pvt = mci->pvt_info; in setup_mci_misc_attrs()
3569 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; in setup_mci_misc_attrs()
3570 mci->edac_ctl_cap = EDAC_FLAG_NONE; in setup_mci_misc_attrs()
3572 if (pvt->umc) { in setup_mci_misc_attrs()
3575 if (pvt->nbcap & NBCAP_SECDED) in setup_mci_misc_attrs()
3576 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in setup_mci_misc_attrs()
3578 if (pvt->nbcap & NBCAP_CHIPKILL) in setup_mci_misc_attrs()
3579 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in setup_mci_misc_attrs()
3582 mci->edac_cap = determine_edac_cap(pvt); in setup_mci_misc_attrs()
3583 mci->mod_name = EDAC_MOD_STR; in setup_mci_misc_attrs()
3584 mci->ctl_name = fam_type->ctl_name; in setup_mci_misc_attrs()
3585 mci->dev_name = pci_name(pvt->F3); in setup_mci_misc_attrs()
3586 mci->ctl_page_to_phys = NULL; in setup_mci_misc_attrs()
3589 mci->set_sdram_scrub_rate = set_scrub_rate; in setup_mci_misc_attrs()
3590 mci->get_sdram_scrub_rate = get_scrub_rate; in setup_mci_misc_attrs()
3598 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3599 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3600 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3601 pvt->fam = boot_cpu_data.x86; in per_family_init()
3603 switch (pvt->fam) { in per_family_init()
3606 pvt->ops = &family_types[K8_CPUS].ops; in per_family_init()
3611 pvt->ops = &family_types[F10_CPUS].ops; in per_family_init()
3615 if (pvt->model == 0x30) { in per_family_init()
3617 pvt->ops = &family_types[F15_M30H_CPUS].ops; in per_family_init()
3619 } else if (pvt->model == 0x60) { in per_family_init()
3621 pvt->ops = &family_types[F15_M60H_CPUS].ops; in per_family_init()
3624 } else if (pvt->model == 0x13) { in per_family_init()
3628 pvt->ops = &family_types[F15_CPUS].ops; in per_family_init()
3633 if (pvt->model == 0x30) { in per_family_init()
3635 pvt->ops = &family_types[F16_M30H_CPUS].ops; in per_family_init()
3639 pvt->ops = &family_types[F16_CPUS].ops; in per_family_init()
3643 if (pvt->model >= 0x10 && pvt->model <= 0x2f) { in per_family_init()
3645 pvt->ops = &family_types[F17_M10H_CPUS].ops; in per_family_init()
3647 } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { in per_family_init()
3649 pvt->ops = &family_types[F17_M30H_CPUS].ops; in per_family_init()
3651 } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { in per_family_init()
3653 pvt->ops = &family_types[F17_M60H_CPUS].ops; in per_family_init()
3655 } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { in per_family_init()
3657 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3663 pvt->ops = &family_types[F17_CPUS].ops; in per_family_init()
3665 if (pvt->fam == 0x18) in per_family_init()
3670 if (pvt->model >= 0x20 && pvt->model <= 0x2f) { in per_family_init()
3672 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3673 fam_type->ctl_name = "F19h_M20h"; in per_family_init()
3677 pvt->ops = &family_types[F19_CPUS].ops; in per_family_init()
3702 if (pvt->fam >= 0x17) { in hw_info_get()
3703 pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in hw_info_get()
3704 if (!pvt->umc) in hw_info_get()
3705 return -ENOMEM; in hw_info_get()
3707 pci_id1 = fam_type->f0_id; in hw_info_get()
3708 pci_id2 = fam_type->f6_id; in hw_info_get()
3710 pci_id1 = fam_type->f1_id; in hw_info_get()
3711 pci_id2 = fam_type->f2_id; in hw_info_get()
3725 if (pvt->F0 || pvt->F1) in hw_info_put()
3728 kfree(pvt->umc); in hw_info_put()
3735 int ret = -EINVAL; in init_one_instance()
3738 * We need to determine how many memory channels there are. Then use in init_one_instance()
3742 pvt->channel_count = pvt->ops->early_channel_count(pvt); in init_one_instance()
3743 if (pvt->channel_count < 0) in init_one_instance()
3746 ret = -ENOMEM; in init_one_instance()
3748 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
3757 layers[1].size = fam_type->max_mcs; in init_one_instance()
3760 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3764 mci->pvt_info = pvt; in init_one_instance()
3765 mci->pdev = &pvt->F3->dev; in init_one_instance()
3770 mci->edac_cap = EDAC_FLAG_NONE; in init_one_instance()
3772 ret = -ENODEV; in init_one_instance()
3787 for (dct = 0; dct < fam_type->max_mcs; dct++) { in instance_has_memory()
3797 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in probe_one_instance()
3802 ret = -ENOMEM; in probe_one_instance()
3813 pvt->mc_node_id = nid; in probe_one_instance()
3814 pvt->F3 = F3; in probe_one_instance()
3816 ret = -ENODEV; in probe_one_instance()
3832 ret = -ENODEV; in probe_one_instance()
3838 amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS."); in probe_one_instance()
3841 amd64_warn("Forcing ECC on!\n"); in probe_one_instance()
3857 amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, in probe_one_instance()
3858 (pvt->fam == 0xf ? in probe_one_instance()
3859 (pvt->ext_model >= K8_REV_F ? "revF or later " in probe_one_instance()
3861 : ""), pvt->mc_node_id); in probe_one_instance()
3881 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in remove_one_instance()
3887 mci = edac_mc_del_mc(&F3->dev); in remove_one_instance()
3891 pvt = mci->pvt_info; in remove_one_instance()
3899 mci->pvt_info = NULL; in remove_one_instance()
3933 int err = -ENODEV; in amd64_edac_init()
3938 return -EBUSY; in amd64_edac_init()
3941 return -ENODEV; in amd64_edac_init()
3944 return -ENODEV; in amd64_edac_init()
3948 err = -ENOMEM; in amd64_edac_init()
3961 while (--i >= 0) in amd64_edac_init()
3969 err = -ENODEV; in amd64_edac_init()
3982 amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR); in amd64_edac_init()
4033 MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "