Lines Matching full:pvt
89 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
93 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
94 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
96 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
113 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
116 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
129 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg()
141 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
142 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
153 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
170 static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval) in __f17h_set_scrubval() argument
179 pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF); in __f17h_set_scrubval()
180 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1); in __f17h_set_scrubval()
182 pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1); in __f17h_set_scrubval()
189 static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate) in __set_scrub_rate() argument
217 if (pvt->umc) { in __set_scrub_rate()
218 __f17h_set_scrubval(pvt, scrubval); in __set_scrub_rate()
219 } else if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
220 f15h_select_dct(pvt, 0); in __set_scrub_rate()
221 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
222 f15h_select_dct(pvt, 1); in __set_scrub_rate()
223 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
225 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
236 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate() local
239 if (pvt->fam == 0xf) in set_scrub_rate()
242 if (pvt->fam == 0x15) { in set_scrub_rate()
244 if (pvt->model < 0x10) in set_scrub_rate()
245 f15h_select_dct(pvt, 0); in set_scrub_rate()
247 if (pvt->model == 0x60) in set_scrub_rate()
250 return __set_scrub_rate(pvt, bw, min_scrubrate); in set_scrub_rate()
255 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate() local
259 if (pvt->umc) { in get_scrub_rate()
260 amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); in get_scrub_rate()
262 amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); in get_scrub_rate()
268 } else if (pvt->fam == 0x15) { in get_scrub_rate()
270 if (pvt->model < 0x10) in get_scrub_rate()
271 f15h_select_dct(pvt, 0); in get_scrub_rate()
273 if (pvt->model == 0x60) in get_scrub_rate()
274 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
276 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
278 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
296 static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) in base_limit_match() argument
308 return ((addr >= get_dram_base(pvt, nid)) && in base_limit_match()
309 (addr <= get_dram_limit(pvt, nid))); in base_limit_match()
321 struct amd64_pvt *pvt; in find_mc_by_sys_addr() local
329 pvt = mci->pvt_info; in find_mc_by_sys_addr()
336 intlv_en = dram_intlv_en(pvt, 0); in find_mc_by_sys_addr()
340 if (base_limit_match(pvt, sys_addr, node_id)) in find_mc_by_sys_addr()
356 if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) in find_mc_by_sys_addr()
364 if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { in find_mc_by_sys_addr()
385 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
391 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
392 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
393 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
402 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
403 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
404 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
405 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
420 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
421 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
424 if (pvt->fam == 0x15) in get_cs_base_and_mask()
441 #define for_each_chip_select(i, dct, pvt) \ argument
442 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
444 #define chip_select_base(i, dct, pvt) \ argument
445 pvt->csels[dct].csbases[i]
447 #define for_each_chip_select_mask(i, dct, pvt) \ argument
448 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
459 struct amd64_pvt *pvt; in input_addr_to_csrow() local
463 pvt = mci->pvt_info; in input_addr_to_csrow()
465 for_each_chip_select(csrow, 0, pvt) { in input_addr_to_csrow()
466 if (!csrow_enabled(csrow, 0, pvt)) in input_addr_to_csrow()
469 get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); in input_addr_to_csrow()
476 pvt->mc_node_id); in input_addr_to_csrow()
482 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
506 struct amd64_pvt *pvt = mci->pvt_info; in get_dram_hole_info() local
509 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in get_dram_hole_info()
511 pvt->ext_model, pvt->mc_node_id); in get_dram_hole_info()
516 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in get_dram_hole_info()
521 if (!dhar_valid(pvt)) { in get_dram_hole_info()
523 pvt->mc_node_id); in get_dram_hole_info()
545 *hole_base = dhar_base(pvt); in get_dram_hole_info()
548 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in get_dram_hole_info()
549 : k8_dhar_offset(pvt); in get_dram_hole_info()
552 pvt->mc_node_id, (unsigned long)*hole_base, in get_dram_hole_info()
564 struct amd64_pvt *pvt = mci->pvt_info; \
566 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
615 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_show() local
616 return sprintf(buf, "0x%x\n", pvt->injection.section); in inject_section_show()
630 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_store() local
643 pvt->injection.section = (u32) value; in inject_section_store()
651 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_show() local
652 return sprintf(buf, "0x%x\n", pvt->injection.word); in inject_word_show()
666 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_store() local
679 pvt->injection.word = (u32) value; in inject_word_store()
688 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_show() local
689 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in inject_ecc_vector_show()
702 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_store() local
715 pvt->injection.bit_map = (u32) value; in inject_ecc_vector_store()
720 * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
728 struct amd64_pvt *pvt = mci->pvt_info; in inject_read_store() local
738 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_read_store()
740 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_read_store()
742 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); in inject_read_store()
745 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_read_store()
753 * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
761 struct amd64_pvt *pvt = mci->pvt_info; in inject_write_store() local
771 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_write_store()
773 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_write_store()
775 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); in inject_write_store()
784 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_write_store()
788 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); in inject_write_store()
824 struct amd64_pvt *pvt = mci->pvt_info; in inj_is_visible() local
827 if (pvt->fam >= 0x10 && pvt->fam <= 0x16) in inj_is_visible()
870 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr() local
874 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
925 struct amd64_pvt *pvt; in dram_addr_to_input_addr() local
929 pvt = mci->pvt_info; in dram_addr_to_input_addr()
935 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); in dram_addr_to_input_addr()
997 static unsigned long determine_edac_cap(struct amd64_pvt *pvt) in determine_edac_cap() argument
1002 if (pvt->umc) { in determine_edac_cap()
1006 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in determine_edac_cap()
1012 if (pvt->umc[i].umc_cfg & BIT(12)) in determine_edac_cap()
1019 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in determine_edac_cap()
1023 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()
1032 static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) in debug_dump_dramcfg_low() argument
1036 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1037 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
1053 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
1072 static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) in f17_get_cs_mode() argument
1076 if (csrow_enabled(2 * dimm, ctrl, pvt)) in f17_get_cs_mode()
1079 if (csrow_enabled(2 * dimm + 1, ctrl, pvt)) in f17_get_cs_mode()
1083 if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt)) in f17_get_cs_mode()
1089 static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes_df() argument
1099 cs_mode = f17_get_cs_mode(dimm, ctrl, pvt); in debug_display_dimm_sizes_df()
1101 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); in debug_display_dimm_sizes_df()
1102 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); in debug_display_dimm_sizes_df()
1110 static void __dump_misc_regs_df(struct amd64_pvt *pvt) in __dump_misc_regs_df() argument
1117 umc = &pvt->umc[i]; in __dump_misc_regs_df()
1124 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp); in __dump_misc_regs_df()
1127 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp); in __dump_misc_regs_df()
1141 if (pvt->dram_type == MEM_LRDDR4) { in __dump_misc_regs_df()
1142 amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp); in __dump_misc_regs_df()
1147 debug_display_dimm_sizes_df(pvt, i); in __dump_misc_regs_df()
1151 pvt->dhar, dhar_base(pvt)); in __dump_misc_regs_df()
1155 static void __dump_misc_regs(struct amd64_pvt *pvt) in __dump_misc_regs() argument
1157 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in __dump_misc_regs()
1160 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in __dump_misc_regs()
1163 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in __dump_misc_regs()
1164 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in __dump_misc_regs()
1166 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in __dump_misc_regs()
1168 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in __dump_misc_regs()
1171 pvt->dhar, dhar_base(pvt), in __dump_misc_regs()
1172 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in __dump_misc_regs()
1173 : f10_dhar_offset(pvt)); in __dump_misc_regs()
1175 debug_display_dimm_sizes(pvt, 0); in __dump_misc_regs()
1178 if (pvt->fam == 0xf) in __dump_misc_regs()
1181 debug_display_dimm_sizes(pvt, 1); in __dump_misc_regs()
1184 if (!dct_ganging_enabled(pvt)) in __dump_misc_regs()
1185 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in __dump_misc_regs()
1189 static void dump_misc_regs(struct amd64_pvt *pvt) in dump_misc_regs() argument
1191 if (pvt->umc) in dump_misc_regs()
1192 __dump_misc_regs_df(pvt); in dump_misc_regs()
1194 __dump_misc_regs(pvt); in dump_misc_regs()
1196 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); in dump_misc_regs()
1198 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dump_misc_regs()
1204 static void prep_chip_selects(struct amd64_pvt *pvt) in prep_chip_selects() argument
1206 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in prep_chip_selects()
1207 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
1208 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in prep_chip_selects()
1209 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in prep_chip_selects()
1210 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in prep_chip_selects()
1211 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in prep_chip_selects()
1212 } else if (pvt->fam >= 0x17) { in prep_chip_selects()
1216 pvt->csels[umc].b_cnt = 4; in prep_chip_selects()
1217 pvt->csels[umc].m_cnt = 2; in prep_chip_selects()
1221 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in prep_chip_selects()
1222 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in prep_chip_selects()
1226 static void read_umc_base_mask(struct amd64_pvt *pvt) in read_umc_base_mask() argument
1240 for_each_chip_select(cs, umc, pvt) { in read_umc_base_mask()
1241 base = &pvt->csels[umc].csbases[cs]; in read_umc_base_mask()
1242 base_sec = &pvt->csels[umc].csbases_sec[cs]; in read_umc_base_mask()
1247 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) in read_umc_base_mask()
1251 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) in read_umc_base_mask()
1259 for_each_chip_select_mask(cs, umc, pvt) { in read_umc_base_mask()
1260 mask = &pvt->csels[umc].csmasks[cs]; in read_umc_base_mask()
1261 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in read_umc_base_mask()
1266 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) in read_umc_base_mask()
1270 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) in read_umc_base_mask()
1280 static void read_dct_base_mask(struct amd64_pvt *pvt) in read_dct_base_mask() argument
1284 prep_chip_selects(pvt); in read_dct_base_mask()
1286 if (pvt->umc) in read_dct_base_mask()
1287 return read_umc_base_mask(pvt); in read_dct_base_mask()
1289 for_each_chip_select(cs, 0, pvt) { in read_dct_base_mask()
1292 u32 *base0 = &pvt->csels[0].csbases[cs]; in read_dct_base_mask()
1293 u32 *base1 = &pvt->csels[1].csbases[cs]; in read_dct_base_mask()
1295 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) in read_dct_base_mask()
1299 if (pvt->fam == 0xf) in read_dct_base_mask()
1302 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) in read_dct_base_mask()
1304 cs, *base1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1308 for_each_chip_select_mask(cs, 0, pvt) { in read_dct_base_mask()
1311 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in read_dct_base_mask()
1312 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in read_dct_base_mask()
1314 if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) in read_dct_base_mask()
1318 if (pvt->fam == 0xf) in read_dct_base_mask()
1321 if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) in read_dct_base_mask()
1323 cs, *mask1, (pvt->fam == 0x10) ? reg1 in read_dct_base_mask()
1328 static void determine_memory_type(struct amd64_pvt *pvt) in determine_memory_type() argument
1332 if (pvt->umc) { in determine_memory_type()
1333 if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) in determine_memory_type()
1334 pvt->dram_type = MEM_LRDDR4; in determine_memory_type()
1335 else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) in determine_memory_type()
1336 pvt->dram_type = MEM_RDDR4; in determine_memory_type()
1338 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1342 switch (pvt->fam) { in determine_memory_type()
1344 if (pvt->ext_model >= K8_REV_F) in determine_memory_type()
1347 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()
1351 if (pvt->dchr0 & DDR3_MODE) in determine_memory_type()
1354 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()
1358 if (pvt->model < 0x60) in determine_memory_type()
1370 amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); in determine_memory_type()
1371 dcsm = pvt->csels[0].csmasks[0]; in determine_memory_type()
1374 pvt->dram_type = MEM_DDR4; in determine_memory_type()
1375 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()
1376 pvt->dram_type = MEM_DDR3; in determine_memory_type()
1378 pvt->dram_type = MEM_LRDDR3; in determine_memory_type()
1380 pvt->dram_type = MEM_RDDR3; in determine_memory_type()
1388 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in determine_memory_type()
1389 pvt->dram_type = MEM_EMPTY; in determine_memory_type()
1394 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()
1398 static int k8_early_channel_count(struct amd64_pvt *pvt) in k8_early_channel_count() argument
1402 if (pvt->ext_model >= K8_REV_F) in k8_early_channel_count()
1404 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()
1407 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()
1410 pvt->dclr1 = 0; in k8_early_channel_count()
1416 static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) in get_error_address() argument
1428 pvt = mci->pvt_info; in get_error_address()
1430 if (pvt->fam == 0xf) { in get_error_address()
1440 if (pvt->fam == 0x15) { in get_error_address()
1449 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1464 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1497 static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) in read_dram_base_limit_regs() argument
1505 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1506 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1508 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1511 if (!dram_rw(pvt, range)) in read_dram_base_limit_regs()
1514 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1515 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1518 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1521 nb = node_to_amd_nb(dram_dst_node(pvt, range)); in read_dram_base_limit_regs()
1525 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1527 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1538 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1541 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1543 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1546 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1554 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow() local
1578 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1619 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1622 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1624 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1628 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1674 static int f1x_early_channel_count(struct amd64_pvt *pvt) in f1x_early_channel_count() argument
1679 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()
1698 u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); in f1x_early_channel_count()
1716 static int f17_early_channel_count(struct amd64_pvt *pvt) in f17_early_channel_count() argument
1722 channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT); in f17_early_channel_count()
1786 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1789 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1793 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1802 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1811 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1815 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1819 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1824 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1844 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
1856 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in f17_addr_mask_to_cs_size() argument
1884 addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm]; in f17_addr_mask_to_cs_size()
1886 addr_mask_orig = pvt->csels[umc].csmasks[dimm]; in f17_addr_mask_to_cs_size()
1913 static void read_dram_ctl_register(struct amd64_pvt *pvt) in read_dram_ctl_register() argument
1916 if (pvt->fam == 0xf) in read_dram_ctl_register()
1919 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
1921 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
1924 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); in read_dram_ctl_register()
1926 if (!dct_ganging_enabled(pvt)) in read_dram_ctl_register()
1928 (dct_high_range_enabled(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1931 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1932 (dct_memory_cleared(pvt) ? "yes" : "no")); in read_dram_ctl_register()
1936 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), in read_dram_ctl_register()
1937 dct_sel_interleave_addr(pvt)); in read_dram_ctl_register()
1940 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
1947 static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f15_m30h_determine_channel() argument
1961 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_determine_channel()
1978 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, in f1x_determine_channel() argument
1981 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
1983 if (dct_ganging_enabled(pvt)) in f1x_determine_channel()
1992 if (dct_interleave_enabled(pvt)) { in f1x_determine_channel()
1993 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f1x_determine_channel()
2015 if (dct_high_range_enabled(pvt)) in f1x_determine_channel()
2022 static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, in f1x_get_norm_dct_addr() argument
2027 u64 dram_base = get_dram_base(pvt, range); in f1x_get_norm_dct_addr()
2028 u64 hole_off = f10_dhar_offset(pvt); in f1x_get_norm_dct_addr()
2029 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
2044 dct_sel_base_addr < dhar_base(pvt)) && in f1x_get_norm_dct_addr()
2045 dhar_valid(pvt) && in f1x_get_norm_dct_addr()
2060 if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) in f1x_get_norm_dct_addr()
2073 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
2077 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
2078 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
2080 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
2081 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
2101 struct amd64_pvt *pvt; in f1x_lookup_addr_in_dct() local
2110 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
2114 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
2115 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
2118 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2129 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
2133 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
2147 static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) in f1x_swap_interleaved_region() argument
2151 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
2153 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
2157 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
2177 static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f1x_match_to_this_node() argument
2186 u8 node_id = dram_dst_node(pvt, range); in f1x_match_to_this_node()
2187 u8 intlv_en = dram_intlv_en(pvt, range); in f1x_match_to_this_node()
2188 u32 intlv_sel = dram_intlv_sel(pvt, range); in f1x_match_to_this_node()
2191 range, sys_addr, get_dram_limit(pvt, range)); in f1x_match_to_this_node()
2193 if (dhar_valid(pvt) && in f1x_match_to_this_node()
2194 dhar_base(pvt) <= sys_addr && in f1x_match_to_this_node()
2204 sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); in f1x_match_to_this_node()
2206 dct_sel_base = dct_sel_baseaddr(pvt); in f1x_match_to_this_node()
2212 if (dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
2213 !dct_ganging_enabled(pvt) && in f1x_match_to_this_node()
2217 channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); in f1x_match_to_this_node()
2219 chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, in f1x_match_to_this_node()
2228 if (dct_interleave_enabled(pvt) && in f1x_match_to_this_node()
2229 !dct_high_range_enabled(pvt) && in f1x_match_to_this_node()
2230 !dct_ganging_enabled(pvt)) { in f1x_match_to_this_node()
2232 if (dct_sel_interleave_addr(pvt) != 1) { in f1x_match_to_this_node()
2233 if (dct_sel_interleave_addr(pvt) == 0x3) in f1x_match_to_this_node()
2257 static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, in f15_m30h_match_to_this_node() argument
2267 u64 dhar_offset = f10_dhar_offset(pvt); in f15_m30h_match_to_this_node()
2268 u8 intlv_addr = dct_sel_interleave_addr(pvt); in f15_m30h_match_to_this_node()
2269 u8 node_id = dram_dst_node(pvt, range); in f15_m30h_match_to_this_node()
2270 u8 intlv_en = dram_intlv_en(pvt, range); in f15_m30h_match_to_this_node()
2272 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2273 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2279 range, sys_addr, get_dram_limit(pvt, range)); in f15_m30h_match_to_this_node()
2281 if (!(get_dram_base(pvt, range) <= sys_addr) && in f15_m30h_match_to_this_node()
2282 !(get_dram_limit(pvt, range) >= sys_addr)) in f15_m30h_match_to_this_node()
2285 if (dhar_valid(pvt) && in f15_m30h_match_to_this_node()
2286 dhar_base(pvt) <= sys_addr && in f15_m30h_match_to_this_node()
2294 dct_base = (u64) dct_sel_baseaddr(pvt); in f15_m30h_match_to_this_node()
2308 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2309 channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en); in f15_m30h_match_to_this_node()
2311 channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, in f15_m30h_match_to_this_node()
2351 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2357 f15h_select_dct(pvt, channel); in f15_m30h_match_to_this_node()
2366 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2379 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, in f1x_translate_sysaddr_to_cs() argument
2387 if (!dram_rw(pvt, range)) in f1x_translate_sysaddr_to_cs()
2390 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2391 cs_found = f15_m30h_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2395 else if ((get_dram_base(pvt, range) <= sys_addr) && in f1x_translate_sysaddr_to_cs()
2396 (get_dram_limit(pvt, range) >= sys_addr)) { in f1x_translate_sysaddr_to_cs()
2397 cs_found = f1x_match_to_this_node(pvt, range, in f1x_translate_sysaddr_to_cs()
2416 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow() local
2420 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2431 if (dct_ganging_enabled(pvt)) in f1x_map_sysaddr_to_csrow()
2439 static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) in debug_display_dimm_sizes() argument
2442 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in debug_display_dimm_sizes()
2443 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in debug_display_dimm_sizes()
2445 if (pvt->fam == 0xf) { in debug_display_dimm_sizes()
2447 if (pvt->ext_model < K8_REV_F) in debug_display_dimm_sizes()
2453 if (pvt->fam == 0x10) { in debug_display_dimm_sizes()
2454 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in debug_display_dimm_sizes()
2455 : pvt->dbam0; in debug_display_dimm_sizes()
2456 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? in debug_display_dimm_sizes()
2457 pvt->csels[1].csbases : in debug_display_dimm_sizes()
2458 pvt->csels[0].csbases; in debug_display_dimm_sizes()
2460 dbam = pvt->dbam0; in debug_display_dimm_sizes()
2461 dcsb = pvt->csels[1].csbases; in debug_display_dimm_sizes()
2479 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2485 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in debug_display_dimm_sizes()
2772 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome() local
2775 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2778 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2779 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2782 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2784 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2788 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2841 struct amd64_pvt *pvt; in decode_bus_error() local
2852 pvt = mci->pvt_info; in decode_bus_error()
2864 sys_addr = get_error_address(pvt, m); in decode_bus_error()
2869 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2892 struct amd64_pvt *pvt; in decode_umc_error() local
2900 pvt = mci->pvt_info; in decode_umc_error()
2925 if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) { in decode_umc_error()
2937 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2942 reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2) in reserve_mc_sibling_devs() argument
2944 if (pvt->umc) { in reserve_mc_sibling_devs()
2945 pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2946 if (!pvt->F0) { in reserve_mc_sibling_devs()
2951 pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2952 if (!pvt->F6) { in reserve_mc_sibling_devs()
2953 pci_dev_put(pvt->F0); in reserve_mc_sibling_devs()
2954 pvt->F0 = NULL; in reserve_mc_sibling_devs()
2961 pci_ctl_dev = &pvt->F0->dev; in reserve_mc_sibling_devs()
2963 edac_dbg(1, "F0: %s\n", pci_name(pvt->F0)); in reserve_mc_sibling_devs()
2964 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2965 edac_dbg(1, "F6: %s\n", pci_name(pvt->F6)); in reserve_mc_sibling_devs()
2971 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2972 if (!pvt->F1) { in reserve_mc_sibling_devs()
2978 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2979 if (!pvt->F2) { in reserve_mc_sibling_devs()
2980 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2981 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2988 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2990 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2991 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2992 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2997 static void free_mc_sibling_devs(struct amd64_pvt *pvt) in free_mc_sibling_devs() argument
2999 if (pvt->umc) { in free_mc_sibling_devs()
3000 pci_dev_put(pvt->F0); in free_mc_sibling_devs()
3001 pci_dev_put(pvt->F6); in free_mc_sibling_devs()
3003 pci_dev_put(pvt->F1); in free_mc_sibling_devs()
3004 pci_dev_put(pvt->F2); in free_mc_sibling_devs()
3008 static void determine_ecc_sym_sz(struct amd64_pvt *pvt) in determine_ecc_sym_sz() argument
3010 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
3012 if (pvt->umc) { in determine_ecc_sym_sz()
3017 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in determine_ecc_sym_sz()
3018 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
3019 pvt->ecc_sym_sz = 16; in determine_ecc_sym_sz()
3021 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
3022 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
3027 } else if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
3030 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
3032 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
3033 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
3036 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
3037 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
3044 static void __read_mc_regs_df(struct amd64_pvt *pvt) in __read_mc_regs_df() argument
3046 u8 nid = pvt->mc_node_id; in __read_mc_regs_df()
3054 umc = &pvt->umc[i]; in __read_mc_regs_df()
3068 static void read_mc_regs(struct amd64_pvt *pvt) in read_mc_regs() argument
3077 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in read_mc_regs()
3078 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in read_mc_regs()
3083 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in read_mc_regs()
3084 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in read_mc_regs()
3089 if (pvt->umc) { in read_mc_regs()
3090 __read_mc_regs_df(pvt); in read_mc_regs()
3091 amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar); in read_mc_regs()
3096 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in read_mc_regs()
3098 read_dram_ctl_register(pvt); in read_mc_regs()
3104 read_dram_base_limit_regs(pvt, range); in read_mc_regs()
3106 rw = dram_rw(pvt, range); in read_mc_regs()
3112 get_dram_base(pvt, range), in read_mc_regs()
3113 get_dram_limit(pvt, range)); in read_mc_regs()
3116 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", in read_mc_regs()
3119 dram_intlv_sel(pvt, range), in read_mc_regs()
3120 dram_dst_node(pvt, range)); in read_mc_regs()
3123 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in read_mc_regs()
3124 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in read_mc_regs()
3126 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in read_mc_regs()
3128 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in read_mc_regs()
3129 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in read_mc_regs()
3131 if (!dct_ganging_enabled(pvt)) { in read_mc_regs()
3132 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in read_mc_regs()
3133 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in read_mc_regs()
3137 read_dct_base_mask(pvt); in read_mc_regs()
3139 determine_memory_type(pvt); in read_mc_regs()
3140 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in read_mc_regs()
3142 determine_ecc_sym_sz(pvt); in read_mc_regs()
3179 static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in get_csrow_nr_pages() argument
3181 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in get_csrow_nr_pages()
3185 if (!pvt->umc) { in get_csrow_nr_pages()
3189 cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt); in get_csrow_nr_pages()
3192 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in get_csrow_nr_pages()
3204 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows_df() local
3225 for_each_chip_select(cs, umc, pvt) { in init_csrows_df()
3226 if (!csrow_enabled(cs, umc, pvt)) in init_csrows_df()
3233 pvt->mc_node_id, cs); in init_csrows_df()
3235 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); in init_csrows_df()
3236 dimm->mtype = pvt->dram_type; in init_csrows_df()
3252 struct amd64_pvt *pvt = mci->pvt_info; in init_csrows() local
3260 if (pvt->umc) in init_csrows()
3263 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in init_csrows()
3265 pvt->nbcfg = val; in init_csrows()
3268 pvt->mc_node_id, val, in init_csrows()
3274 for_each_chip_select(i, 0, pvt) { in init_csrows()
3275 bool row_dct0 = !!csrow_enabled(i, 0, pvt); in init_csrows()
3278 if (pvt->fam != 0xf) in init_csrows()
3279 row_dct1 = !!csrow_enabled(i, 1, pvt); in init_csrows()
3288 pvt->mc_node_id, i); in init_csrows()
3291 nr_pages = get_csrow_nr_pages(pvt, 0, i); in init_csrows()
3296 if (pvt->fam != 0xf && row_dct1) { in init_csrows()
3297 int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i); in init_csrows()
3306 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in init_csrows()
3307 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in init_csrows()
3312 for (j = 0; j < pvt->channel_count; j++) { in init_csrows()
3314 dimm->mtype = pvt->dram_type; in init_csrows()
3483 static bool ecc_enabled(struct amd64_pvt *pvt) in ecc_enabled() argument
3485 u16 nid = pvt->mc_node_id; in ecc_enabled()
3495 umc = &pvt->umc[i]; in ecc_enabled()
3516 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in ecc_enabled()
3535 f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) in f17h_determine_edac_ctl_cap() argument
3540 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in f17h_determine_edac_ctl_cap()
3541 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in f17h_determine_edac_ctl_cap()
3542 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in f17h_determine_edac_ctl_cap()
3544 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in f17h_determine_edac_ctl_cap()
3545 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in f17h_determine_edac_ctl_cap()
3567 struct amd64_pvt *pvt = mci->pvt_info; in setup_mci_misc_attrs() local
3572 if (pvt->umc) { in setup_mci_misc_attrs()
3573 f17h_determine_edac_ctl_cap(mci, pvt); in setup_mci_misc_attrs()
3575 if (pvt->nbcap & NBCAP_SECDED) in setup_mci_misc_attrs()
3578 if (pvt->nbcap & NBCAP_CHIPKILL) in setup_mci_misc_attrs()
3582 mci->edac_cap = determine_edac_cap(pvt); in setup_mci_misc_attrs()
3585 mci->dev_name = pci_name(pvt->F3); in setup_mci_misc_attrs()
3596 static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) in per_family_init() argument
3598 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3599 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3600 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3601 pvt->fam = boot_cpu_data.x86; in per_family_init()
3603 switch (pvt->fam) { in per_family_init()
3606 pvt->ops = &family_types[K8_CPUS].ops; in per_family_init()
3611 pvt->ops = &family_types[F10_CPUS].ops; in per_family_init()
3615 if (pvt->model == 0x30) { in per_family_init()
3617 pvt->ops = &family_types[F15_M30H_CPUS].ops; in per_family_init()
3619 } else if (pvt->model == 0x60) { in per_family_init()
3621 pvt->ops = &family_types[F15_M60H_CPUS].ops; in per_family_init()
3624 } else if (pvt->model == 0x13) { in per_family_init()
3628 pvt->ops = &family_types[F15_CPUS].ops; in per_family_init()
3633 if (pvt->model == 0x30) { in per_family_init()
3635 pvt->ops = &family_types[F16_M30H_CPUS].ops; in per_family_init()
3639 pvt->ops = &family_types[F16_CPUS].ops; in per_family_init()
3643 if (pvt->model >= 0x10 && pvt->model <= 0x2f) { in per_family_init()
3645 pvt->ops = &family_types[F17_M10H_CPUS].ops; in per_family_init()
3647 } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) { in per_family_init()
3649 pvt->ops = &family_types[F17_M30H_CPUS].ops; in per_family_init()
3651 } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) { in per_family_init()
3653 pvt->ops = &family_types[F17_M60H_CPUS].ops; in per_family_init()
3655 } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) { in per_family_init()
3657 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3663 pvt->ops = &family_types[F17_CPUS].ops; in per_family_init()
3665 if (pvt->fam == 0x18) in per_family_init()
3670 if (pvt->model >= 0x20 && pvt->model <= 0x2f) { in per_family_init()
3672 pvt->ops = &family_types[F17_M70H_CPUS].ops; in per_family_init()
3677 pvt->ops = &family_types[F19_CPUS].ops; in per_family_init()
3697 static int hw_info_get(struct amd64_pvt *pvt) in hw_info_get() argument
3702 if (pvt->fam >= 0x17) { in hw_info_get()
3703 pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in hw_info_get()
3704 if (!pvt->umc) in hw_info_get()
3714 ret = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2); in hw_info_get()
3718 read_mc_regs(pvt); in hw_info_get()
3723 static void hw_info_put(struct amd64_pvt *pvt) in hw_info_put() argument
3725 if (pvt->F0 || pvt->F1) in hw_info_put()
3726 free_mc_sibling_devs(pvt); in hw_info_put()
3728 kfree(pvt->umc); in hw_info_put()
3731 static int init_one_instance(struct amd64_pvt *pvt) in init_one_instance() argument
3742 pvt->channel_count = pvt->ops->early_channel_count(pvt); in init_one_instance()
3743 if (pvt->channel_count < 0) in init_one_instance()
3748 layers[0].size = pvt->csels[0].b_cnt; in init_one_instance()
3760 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3764 mci->pvt_info = pvt; in init_one_instance()
3765 mci->pdev = &pvt->F3->dev; in init_one_instance()
3782 static bool instance_has_memory(struct amd64_pvt *pvt) in instance_has_memory() argument
3788 for_each_chip_select(cs, dct, pvt) in instance_has_memory()
3789 cs_enabled |= csrow_enabled(cs, dct, pvt); in instance_has_memory()
3798 struct amd64_pvt *pvt = NULL; in probe_one_instance() local
3809 pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); in probe_one_instance()
3810 if (!pvt) in probe_one_instance()
3813 pvt->mc_node_id = nid; in probe_one_instance()
3814 pvt->F3 = F3; in probe_one_instance()
3817 fam_type = per_family_init(pvt); in probe_one_instance()
3821 ret = hw_info_get(pvt); in probe_one_instance()
3826 if (!instance_has_memory(pvt)) { in probe_one_instance()
3831 if (!ecc_enabled(pvt)) { in probe_one_instance()
3847 ret = init_one_instance(pvt); in probe_one_instance()
3858 (pvt->fam == 0xf ? in probe_one_instance()
3859 (pvt->ext_model >= K8_REV_F ? "revF or later " in probe_one_instance()
3861 : ""), pvt->mc_node_id); in probe_one_instance()
3863 dump_misc_regs(pvt); in probe_one_instance()
3868 hw_info_put(pvt); in probe_one_instance()
3869 kfree(pvt); in probe_one_instance()
3884 struct amd64_pvt *pvt; in remove_one_instance() local
3891 pvt = mci->pvt_info; in remove_one_instance()
3901 hw_info_put(pvt); in remove_one_instance()
3902 kfree(pvt); in remove_one_instance()