Lines Matching +full:system +full:- +full:cache +full:- +full:controller
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
68 It should be noticed that keeping both GHES and a hardware-driven
92 When enabled, in each of the respective memory controller directories
93 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95 - inject_section (0..3, 16-byte section of 64-byte cacheline),
96 - inject_word (0..8, 16-bit word of 16-byte section),
97 - inject_ecc_vector (hex ecc vector: select bits of inject word)
103 tristate "Amazon's Annapurna Lab Memory Controller"
171 E3-1200 based DRAM controllers.
192 i7 Core (Nehalem) Integrated Memory Controller that exists on
232 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
247 system has non-volatile DIMMs you should also manually
259 system has non-volatile DIMMs you should also manually
267 Pondicherry2 Integrated Memory Controller. This SoC IP is
269 micro-server but may appear on others in the future.
277 client SoC Integrated Memory Controller using In-Band ECC IP.
278 This In-Band ECC is first used on the Elkhart Lake SoC but
303 tristate "Cell Broadband Engine memory controller"
307 Cell Broadband Engine internal memory controller
311 tristate "PPC4xx IBM DDR2 Memory Controller"
315 with the IBM DDR2 memory controller found in various
320 tristate "AMD8131 HyperTransport PCI-X Tunnel"
324 AMD8131 HyperTransport PCI-X Tunnel chip.
338 tristate "IBM CPC925 Memory Controller (PPC970FX)"
342 IBM CPC925 Bridge and Memory Controller, which is
347 tristate "Highbank Memory Controller"
351 Calxeda Highbank memory controller.
354 tristate "Highbank L2 Cache"
358 Calxeda Highbank memory controller.
375 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
382 tristate "Cavium Octeon PCI Controller"
394 Cavium ThunderX memory controllers (LMC), Cache
395 Coherent Processor Interconnect (CCPI) and L2 cache
416 bool "Altera L2 Cache ECC"
420 Altera L2 cache Memory for Altera SoCs. This option
421 requires L2 cache.
424 bool "Altera On-Chip RAM ECC"
428 Altera On-Chip RAM Memory for Altera SoCs.
479 bool "Marvell Armada XP DDR and L2 Cache ECC"
483 DDR RAM and L2 cache controllers.
486 tristate "Synopsys DDR Memory Controller"
490 memory controller.
493 tristate "APM X-Gene SoC"
497 APM X-Gene family of SOCs.
500 tristate "Texas Instruments DDR3 ECC Controller"
506 tristate "QCOM EDAC Controller"
513 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
516 For debugging issues having to do with stability and overall system
536 tristate "ARM DMC-520 ECC"
540 SoCs with ARM DMC-520 DRAM controller.