Lines Matching full:on
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
38 This turns on debugging information for the entire EDAC subsystem.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
49 occurring on your machine in human-readable form.
57 depends on ACPI_APEI_GHES && (EDAC=y)
79 depends on AMD_NB && EDAC_DECODE_MCE
81 Support for error detection and correction of DRAM ECC errors on
104 depends on (ARCH_ALPINE || COMPILE_TEST)
111 depends on PCI && X86_32
113 Support for error detection and correction on the AMD 76x
118 depends on PCI && X86_32
120 Support for error detection and correction on the Intel
125 depends on PCI && X86
127 Support for error detection and correction on the Intel
132 depends on PCI && X86_32
133 depends on BROKEN
135 Support for error detection and correction on the Intel
140 depends on PCI && X86_32
142 Support for error detection and correction on the Intel
147 depends on PCI && X86
149 Support for error detection and correction on the Intel
154 depends on PCI && X86
156 Support for error detection and correction on the Intel
161 depends on PCI && X86
163 Support for error detection and correction on the Intel
168 depends on PCI && X86
170 Support for error detection and correction on the Intel
175 depends on PCI && X86
177 Support for error detection and correction on the Intel
182 depends on PCI && X86
189 depends on PCI && X86 && X86_MCE_INTEL
192 i7 Core (Nehalem) Integrated Memory Controller that exists on
198 depends on PCI && X86_32
200 Support for error detection and correction on the Intel
205 depends on PCI && X86_32
207 Support for error detection and correction on the Radisys
212 depends on X86 && PCI
219 depends on X86 && PCI
226 depends on X86 && PCI
233 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
240 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
241 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
252 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
253 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
264 depends on PCI && X86_64 && X86_MCE_INTEL
266 Support for error detection and correction on the Intel
268 first used on the Apollo Lake platform and Denverton
269 micro-server but may appear on others in the future.
273 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
274 depends on X86_64 && X86_MCE_INTEL
276 Support for error detection and correction on the Intel
278 This In-Band ECC is first used on the Elkhart Lake SoC but
279 may appear on others in the future.
283 depends on FSL_SOC && EDAC=y
285 Support for error detection and correction on the Freescale
290 depends on ARCH_LAYERSCAPE || SOC_LS1021A
292 Support for error detection and correction on Freescale memory
293 controllers on Layerscape SoCs.
297 depends on PPC_PASEMI && PCI
299 Support for error detection and correction on PA Semi
304 depends on PPC_CELL_COMMON
306 Support for error detection and correction on the
308 on platform without a hypervisor
312 depends on 4xx
314 This enables support for EDAC on the ECC memory used
321 depends on PCI && PPC_MAPLE
323 Support for error detection and correction on the
326 on some machine other than Maple.
330 depends on PCI && PPC_MAPLE
332 Support for error detection and correction on the
335 on some machine other than Maple.
339 depends on PPC64
341 Support for error detection and correction on the
348 depends on ARCH_HIGHBANK
350 Support for error detection and correction on the
355 depends on ARCH_HIGHBANK
357 Support for error detection and correction on the
362 depends on CPU_CAVIUM_OCTEON
364 Support for error detection and correction on the primary caches of
369 depends on CAVIUM_OCTEON_SOC
371 Support for error detection and correction on the
376 depends on CAVIUM_OCTEON_SOC
378 Support for error detection and correction on the
383 depends on PCI && CAVIUM_OCTEON_SOC
385 Support for error detection and correction on the
390 depends on ARM64
391 depends on PCI
393 Support for error detection and correction on the
400 depends on EDAC=y && ARCH_INTEL_SOCFPGA
402 Support for error detection and correction on the
408 depends on EDAC_ALTERA=y
410 Support for error detection and correction on the
417 depends on EDAC_ALTERA=y && CACHE_L2X0
419 Support for error detection and correction on the
424 bool "Altera On-Chip RAM ECC"
425 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
427 Support for error detection and correction on the
428 Altera On-Chip RAM Memory for Altera SoCs.
432 depends on EDAC_ALTERA=y
434 Support for error detection and correction on the
439 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
441 Support for error detection and correction on the
446 depends on EDAC_ALTERA=y && PL330_DMA=y
448 Support for error detection and correction on the
453 depends on EDAC_ALTERA=y && USB_DWC2
455 Support for error detection and correction on the
460 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
462 Support for error detection and correction on the
467 depends on EDAC_ALTERA=y && MMC_DW
469 Support for error detection and correction on the
474 depends on EDAC=y && SIFIVE_L2
476 Support for error detection and correction on the SiFive SoCs.
480 depends on MACH_MVEBU_V7
482 Support for error correction and detection on the Marvell Aramada XP
487 depends on ARCH_ZYNQ || ARCH_ZYNQMP
489 Support for error detection and correction on the Synopsys DDR
494 depends on (ARM64 || COMPILE_TEST)
496 Support for error detection and correction on the
501 depends on ARCH_KEYSTONE || SOC_DRA7XX
503 Support for error detection and correction on the TI SoCs.
507 depends on ARCH_QCOM && QCOM_LLCC
509 Support for error detection and correction on the
521 depends on ARCH_ASPEED
523 Support for error detection and correction on the Aspeed AST BMC SoC.
530 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
532 Support for error detection and correction on the
537 depends on ARM64
539 Support for error detection and correction on the