Lines Matching full:and
4 # Licensed and distributed under the GPL
13 tristate "EDAC (Error Detection And Correction) reporting"
40 levels are 0-4 (from low to high) and by default it is set to 2.
68 It should be noticed that keeping both GHES and a hardware-driven
81 Support for error detection and correction of DRAM ECC errors on
87 AMD CPUs up to and excluding family 0x17 provide for Memory
89 module allows the operator/user to inject Uncorrectable and
99 In addition, there are two control files, inject_read and inject_write,
100 which trigger the DRAM ECC Read and Write respectively.
106 Support for error detection and correction for Amazon's Annapurna
107 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
113 Support for error detection and correction on the AMD 76x
120 Support for error detection and correction on the Intel
121 E7205, E7500, E7501 and E7505 server chipsets.
124 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
127 Support for error detection and correction on the Intel
135 Support for error detection and correction on the Intel
142 Support for error detection and correction on the Intel
143 DP82785P and E7210 server chipsets.
149 Support for error detection and correction on the Intel
156 Support for error detection and correction on the Intel
157 3000 and 3010 server chipsets.
163 Support for error detection and correction on the Intel
164 3200 and 3210 server chipsets.
170 Support for error detection and correction on the Intel
177 Support for error detection and correction on the Intel
184 Support for error detection and correction the Intel
191 Support for error detection and correction the Intel
194 and Xeon 55xx processors.
200 Support for error detection and correction on the Intel
207 Support for error detection and correction on the Radisys
214 Support for error detection and correction the Intel
221 Support for error detection and correction the Intel
228 Support for error detection and correction the Intel
235 Support for error detection and correction the Intel
236 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
245 Support for error detection and correction the Intel
257 Support for error detection and correction the Intel
266 Support for error detection and correction on the Intel
268 first used on the Apollo Lake platform and Denverton
276 Support for error detection and correction on the Intel
285 Support for error detection and correction on the Freescale
292 Support for error detection and correction on Freescale memory
299 Support for error detection and correction on PA Semi
306 Support for error detection and correction on the
317 440SP, 440SPe, 460EX, 460GT and 460SX.
323 Support for error detection and correction on the
332 Support for error detection and correction on the
341 Support for error detection and correction on the
342 IBM CPC925 Bridge and Memory Controller, which is
350 Support for error detection and correction on the
357 Support for error detection and correction on the
364 Support for error detection and correction on the primary caches of
371 Support for error detection and correction on the
378 Support for error detection and correction on the
385 Support for error detection and correction on the
393 Support for error detection and correction on the
395 Coherent Processor Interconnect (CCPI) and L2 cache
402 Support for error detection and correction on the
410 Support for error detection and correction on the
419 Support for error detection and correction on the
427 Support for error detection and correction on the
434 Support for error detection and correction on the
441 Support for error detection and correction on the
448 Support for error detection and correction on the
455 Support for error detection and correction on the
462 Support for error detection and correction on the
469 Support for error detection and correction on the
476 Support for error detection and correction on the SiFive SoCs.
479 bool "Marvell Armada XP DDR and L2 Cache ECC"
482 Support for error correction and detection on the Marvell Aramada XP
483 DDR RAM and L2 cache controllers.
489 Support for error detection and correction on the Synopsys DDR
496 Support for error detection and correction on the
503 Support for error detection and correction on the TI SoCs.
509 Support for error detection and correction on the
512 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
514 of Tag RAM and Data RAM.
516 For debugging issues having to do with stability and overall system
523 Support for error detection and correction on the Aspeed AST BMC SoC.
532 Support for error detection and correction on the
539 Support for error detection and correction on the