547 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg,  in dma_ctrl_write()  function
556 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr);  in dma_ctrl_clr()
562 	dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set);  in dma_ctrl_set()
597 		dma_ctrl_write(chan, reg, addr);  in xilinx_write()
1375 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_vdma_start_transfer()
1460 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);  in xilinx_cdma_start_transfer()
1493 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_cdma_start_transfer()
1534 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_start_transfer()
1567 		dma_ctrl_write(chan, XILINX_DMA_REG_BTT,  in xilinx_dma_start_transfer()
1616 	dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);  in xilinx_mcdma_start_transfer()
1625 	dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg);  in xilinx_mcdma_start_transfer()
1630 	dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);  in xilinx_mcdma_start_transfer()
1789 	dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest),  in xilinx_mcdma_irq_handler()
1840 	dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
1853 		dma_ctrl_write(chan, XILINX_DMA_REG_DMASR,  in xilinx_dma_irq_handler()
2318 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_prep_dma_cyclic()
2467 		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);  in xilinx_dma_terminate_all()
2550 	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr);  in xilinx_vdma_channel_set_config()