Lines Matching refs:hdma_dev
90 struct hisi_dma_dev *hdma_dev; member
136 static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index, in hisi_dma_pause_dma() argument
139 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index * in hisi_dma_pause_dma()
145 static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index, in hisi_dma_enable_dma() argument
148 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index * in hisi_dma_enable_dma()
154 static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index) in hisi_dma_mask_irq() argument
156 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_INT_MSK, qp_index, in hisi_dma_mask_irq()
160 static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index) in hisi_dma_unmask_irq() argument
162 void __iomem *base = hdma_dev->base; in hisi_dma_unmask_irq()
169 static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index) in hisi_dma_do_reset() argument
171 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL1 + index * in hisi_dma_do_reset()
177 static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index) in hisi_dma_reset_qp_point() argument
179 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, index, 0); in hisi_dma_reset_qp_point()
180 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0); in hisi_dma_reset_qp_point()
185 struct hisi_dma_dev *hdma_dev = chan->hdma_dev; in hisi_dma_reset_hw_chan() local
189 hisi_dma_pause_dma(hdma_dev, index, true); in hisi_dma_reset_hw_chan()
190 hisi_dma_enable_dma(hdma_dev, index, false); in hisi_dma_reset_hw_chan()
191 hisi_dma_mask_irq(hdma_dev, index); in hisi_dma_reset_hw_chan()
193 ret = readl_relaxed_poll_timeout(hdma_dev->base + in hisi_dma_reset_hw_chan()
197 dev_err(&hdma_dev->pdev->dev, "disable channel timeout!\n"); in hisi_dma_reset_hw_chan()
201 hisi_dma_do_reset(hdma_dev, index); in hisi_dma_reset_hw_chan()
202 hisi_dma_reset_qp_point(hdma_dev, index); in hisi_dma_reset_hw_chan()
203 hisi_dma_pause_dma(hdma_dev, index, false); in hisi_dma_reset_hw_chan()
204 hisi_dma_enable_dma(hdma_dev, index, true); in hisi_dma_reset_hw_chan()
205 hisi_dma_unmask_irq(hdma_dev, index); in hisi_dma_reset_hw_chan()
207 ret = readl_relaxed_poll_timeout(hdma_dev->base + in hisi_dma_reset_hw_chan()
211 dev_err(&hdma_dev->pdev->dev, "reset channel timeout!\n"); in hisi_dma_reset_hw_chan()
219 struct hisi_dma_dev *hdma_dev = chan->hdma_dev; in hisi_dma_free_chan_resources() local
224 memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth); in hisi_dma_free_chan_resources()
225 memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth); in hisi_dma_free_chan_resources()
264 struct hisi_dma_dev *hdma_dev = chan->hdma_dev; in hisi_dma_start_transfer() local
270 dev_err(&hdma_dev->pdev->dev, "no issued task!\n"); in hisi_dma_start_transfer()
288 chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth; in hisi_dma_start_transfer()
291 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, chan->qp_num, in hisi_dma_start_transfer()
316 hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true); in hisi_dma_terminate_all()
327 hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false); in hisi_dma_terminate_all()
339 static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev) in hisi_dma_alloc_qps_mem() argument
341 size_t sq_size = sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth; in hisi_dma_alloc_qps_mem()
342 size_t cq_size = sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth; in hisi_dma_alloc_qps_mem()
343 struct device *dev = &hdma_dev->pdev->dev; in hisi_dma_alloc_qps_mem()
347 for (i = 0; i < hdma_dev->chan_num; i++) { in hisi_dma_alloc_qps_mem()
348 chan = &hdma_dev->chan[i]; in hisi_dma_alloc_qps_mem()
363 static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index) in hisi_dma_init_hw_qp() argument
365 struct hisi_dma_chan *chan = &hdma_dev->chan[index]; in hisi_dma_init_hw_qp()
366 u32 hw_depth = hdma_dev->chan_depth - 1; in hisi_dma_init_hw_qp()
367 void __iomem *base = hdma_dev->base; in hisi_dma_init_hw_qp()
388 static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) in hisi_dma_enable_qp() argument
390 hisi_dma_init_hw_qp(hdma_dev, qp_index); in hisi_dma_enable_qp()
391 hisi_dma_unmask_irq(hdma_dev, qp_index); in hisi_dma_enable_qp()
392 hisi_dma_enable_dma(hdma_dev, qp_index, true); in hisi_dma_enable_qp()
395 static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index) in hisi_dma_disable_qp() argument
397 hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]); in hisi_dma_disable_qp()
400 static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev) in hisi_dma_enable_qps() argument
404 for (i = 0; i < hdma_dev->chan_num; i++) { in hisi_dma_enable_qps()
405 hdma_dev->chan[i].qp_num = i; in hisi_dma_enable_qps()
406 hdma_dev->chan[i].hdma_dev = hdma_dev; in hisi_dma_enable_qps()
407 hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free; in hisi_dma_enable_qps()
408 vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev); in hisi_dma_enable_qps()
409 hisi_dma_enable_qp(hdma_dev, i); in hisi_dma_enable_qps()
413 static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev) in hisi_dma_disable_qps() argument
417 for (i = 0; i < hdma_dev->chan_num; i++) { in hisi_dma_disable_qps()
418 hisi_dma_disable_qp(hdma_dev, i); in hisi_dma_disable_qps()
419 tasklet_kill(&hdma_dev->chan[i].vc.task); in hisi_dma_disable_qps()
426 struct hisi_dma_dev *hdma_dev = chan->hdma_dev; in hisi_dma_irq() local
437 hdma_dev->chan_depth; in hisi_dma_irq()
438 hisi_dma_chan_write(hdma_dev->base, in hisi_dma_irq()
443 dev_err(&hdma_dev->pdev->dev, "task error!\n"); in hisi_dma_irq()
454 static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev) in hisi_dma_request_qps_irq() argument
456 struct pci_dev *pdev = hdma_dev->pdev; in hisi_dma_request_qps_irq()
459 for (i = 0; i < hdma_dev->chan_num; i++) { in hisi_dma_request_qps_irq()
462 &hdma_dev->chan[i]); in hisi_dma_request_qps_irq()
471 static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev) in hisi_dma_enable_hw_channels() argument
475 ret = hisi_dma_alloc_qps_mem(hdma_dev); in hisi_dma_enable_hw_channels()
477 dev_err(&hdma_dev->pdev->dev, "fail to allocate qp memory!\n"); in hisi_dma_enable_hw_channels()
481 ret = hisi_dma_request_qps_irq(hdma_dev); in hisi_dma_enable_hw_channels()
483 dev_err(&hdma_dev->pdev->dev, "fail to request qp irq!\n"); in hisi_dma_enable_hw_channels()
487 hisi_dma_enable_qps(hdma_dev); in hisi_dma_enable_hw_channels()
497 static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev, in hisi_dma_set_mode() argument
500 writel_relaxed(mode == RC ? 1 : 0, hdma_dev->base + HISI_DMA_MODE); in hisi_dma_set_mode()
506 struct hisi_dma_dev *hdma_dev; in hisi_dma_probe() local
530 hdma_dev = devm_kzalloc(dev, struct_size(hdma_dev, chan, HISI_DMA_CHAN_NUM), GFP_KERNEL); in hisi_dma_probe()
531 if (!hdma_dev) in hisi_dma_probe()
534 hdma_dev->base = pcim_iomap_table(pdev)[PCI_BAR_2]; in hisi_dma_probe()
535 hdma_dev->pdev = pdev; in hisi_dma_probe()
536 hdma_dev->chan_num = HISI_DMA_CHAN_NUM; in hisi_dma_probe()
537 hdma_dev->chan_depth = HISI_DMA_Q_DEPTH_VAL; in hisi_dma_probe()
539 pci_set_drvdata(pdev, hdma_dev); in hisi_dma_probe()
550 dma_dev = &hdma_dev->dma_dev; in hisi_dma_probe()
562 hisi_dma_set_mode(hdma_dev, RC); in hisi_dma_probe()
564 ret = hisi_dma_enable_hw_channels(hdma_dev); in hisi_dma_probe()
571 hdma_dev); in hisi_dma_probe()