14 #define DMA_CTL_CH(x)			(0x1000 + (x) * 4)
15 #define DMA_SRC_ADDR_FILLIN(x)		(0x1100 + (x) * 4)
16 #define DMA_DST_ADDR_FILLIN(x)		(0x1200 + (x) * 4)
17 #define DMA_XBAR_SEL(x)			(0x1300 + (x) * 4)
18 #define DMA_REGACCESS_CHID_CFG		(0x1400)
20 #define CTL_CH_TRANSFER_MODE_MASK	GENMASK(1, 0)
21 #define CTL_CH_TRANSFER_MODE_S2S	0
30 #define XBAR_SEL_DEVID_MASK		GENMASK(15, 0)
34 #define REGACCESS_CHID_MASK		GENMASK(2, 0)
41 		return 0;  in idma32_get_slave_devfn()
50 	u32 cfghi = 0, cfglo = 0;  in idma32_initialize_chan_xbar()
130 	cfghi |= IDMA32C_CFGH_DST_PER(dst_id & 0xf);  in idma32_initialize_chan_xbar()
131 	cfghi |= IDMA32C_CFGH_SRC_PER(src_id & 0xf);  in idma32_initialize_chan_xbar()
134 	cfghi |= IDMA32C_CFGH_DST_PER_EXT(dst_id >> 4 & 0x3);  in idma32_initialize_chan_xbar()
135 	cfghi |= IDMA32C_CFGH_SRC_PER_EXT(src_id >> 4 & 0x3);  in idma32_initialize_chan_xbar()
143 	u32 cfghi = 0;  in idma32_initialize_chan_generic()
144 	u32 cfglo = 0;  in idma32_initialize_chan_generic()
150 	cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);  in idma32_initialize_chan_generic()
151 	cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);  in idma32_initialize_chan_generic()
154 	cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);  in idma32_initialize_chan_generic()
155 	cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);  in idma32_initialize_chan_generic()
205 	u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;  in idma32_prepare_ctllo()
206 	u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;  in idma32_prepare_ctllo()
214 	*maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;  in idma32_encode_maxburst()
225  * By default full FIFO (512 bytes) is assigned to channel 0. Here we
232 	u64 fifo_partition = 0;  in idma32_fifo_partition()
234 	/* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */  in idma32_fifo_partition()
235 	fifo_partition |= value << 0;  in idma32_fifo_partition()