Lines Matching full:dmac
136 #define DMAC_ID 0x000 /* R DMAC ID */
137 #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
138 #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
139 #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
140 #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
141 #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
142 #define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
143 #define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
144 #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
145 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
146 #define DMAC_COMMON_INTSTATUS 0x050 /* R DMAC Interrupt Status */
147 #define DMAC_RESET 0x058 /* R DMAC Reset Register1 */
176 #define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
177 #define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
178 #define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
179 #define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
180 #define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
181 #define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
182 #define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
183 #define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
184 #define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */