314 	u32 reg_width, val;  in dw_axi_dma_set_byte_halfword()  local
321 	reg_width = __ffs(chan->config.dst_addr_width);  in dw_axi_dma_set_byte_halfword()
322 	if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)  in dw_axi_dma_set_byte_halfword()
565 	unsigned int reg_width;  in dw_axi_dma_set_hw_desc()  local
586 		reg_width = __ffs(chan->config.dst_addr_width);  in dw_axi_dma_set_hw_desc()
588 		ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |  in dw_axi_dma_set_hw_desc()
595 		reg_width = __ffs(chan->config.src_addr_width);  in dw_axi_dma_set_hw_desc()
597 		ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |  in dw_axi_dma_set_hw_desc()
601 		block_ts = len >> reg_width;  in dw_axi_dma_set_hw_desc()
649 	u32 data_width, reg_width, mem_width;  in calculate_block_len()  local
664 		reg_width = __ffs(chan->config.src_addr_width);  in calculate_block_len()
665 		block_len = axi_block_ts << reg_width;  in calculate_block_len()