Lines Matching full:dw
31 #include "dw-axi-dmac.h"
36 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
184 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { in axi_dma_hw_init()
185 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); in axi_dma_hw_init()
186 axi_chan_disable(&chip->dw->chan[i]); in axi_dma_hw_init()
193 u32 max_width = chan->chip->dw->hdata->m_data_width; in axi_chan_get_xfer_width()
338 u32 priority = chan->chip->dw->hdata->priority[chan->id]; in axi_chan_block_xfer_start()
552 if (desc->chan->chip->dw->hdata->nr_masters > 1) in set_desc_dest_master()
564 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); in dw_axi_dma_set_hw_desc()
573 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; in dw_axi_dma_set_hw_desc()
616 if (chan->chip->dw->hdata->restrict_axi_burst_len) { in dw_axi_dma_set_hw_desc()
617 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; in dw_axi_dma_set_hw_desc()
652 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; in calculate_block_len()
656 data_width = BIT(chan->chip->dw->hdata->m_data_width); in calculate_block_len()
846 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; in dma_chan_prep_dma_memcpy()
887 if (chan->chip->dw->hdata->restrict_axi_burst_len) { in dma_chan_prep_dma_memcpy()
888 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; in dma_chan_prep_dma_memcpy()
1049 struct dw_axi_dma *dw = chip->dw; in dw_axi_dma_interrupt() local
1058 for (i = 0; i < dw->hdata->nr_channels; i++) { in dw_axi_dma_interrupt()
1059 chan = &dw->chan[i]; in dw_axi_dma_interrupt()
1218 struct dw_axi_dma *dw = ofdma->of_dma_data; in dw_axi_dma_of_xlate() local
1222 dchan = dma_get_any_slave_channel(&dw->dma); in dw_axi_dma_of_xlate()
1243 chip->dw->hdata->nr_channels = tmp; in parse_device_properties()
1251 chip->dw->hdata->nr_masters = tmp; in parse_device_properties()
1259 chip->dw->hdata->m_data_width = tmp; in parse_device_properties()
1262 chip->dw->hdata->nr_channels); in parse_device_properties()
1265 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { in parse_device_properties()
1269 chip->dw->hdata->block_size[tmp] = carr[tmp]; in parse_device_properties()
1273 chip->dw->hdata->nr_channels); in parse_device_properties()
1277 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { in parse_device_properties()
1278 if (carr[tmp] >= chip->dw->hdata->nr_channels) in parse_device_properties()
1281 chip->dw->hdata->priority[tmp] = carr[tmp]; in parse_device_properties()
1292 chip->dw->hdata->restrict_axi_burst_len = true; in parse_device_properties()
1293 chip->dw->hdata->axi_rw_burst_len = tmp; in parse_device_properties()
1304 struct dw_axi_dma *dw; in dw_probe() local
1313 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); in dw_probe()
1314 if (!dw) in dw_probe()
1321 chip->dw = dw; in dw_probe()
1323 chip->dw->hdata = hdata; in dw_probe()
1352 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels, in dw_probe()
1353 sizeof(*dw->chan), GFP_KERNEL); in dw_probe()
1354 if (!dw->chan) in dw_probe()
1362 INIT_LIST_HEAD(&dw->dma.channels); in dw_probe()
1364 struct axi_dma_chan *chan = &dw->chan[i]; in dw_probe()
1372 vchan_init(&chan->vc, &dw->dma); in dw_probe()
1376 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); in dw_probe()
1377 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); in dw_probe()
1378 dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask); in dw_probe()
1381 dw->dma.chancnt = hdata->nr_channels; in dw_probe()
1382 dw->dma.max_burst = hdata->axi_rw_burst_len; in dw_probe()
1383 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS; in dw_probe()
1384 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS; in dw_probe()
1385 dw->dma.directions = BIT(DMA_MEM_TO_MEM); in dw_probe()
1386 dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); in dw_probe()
1387 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in dw_probe()
1389 dw->dma.dev = chip->dev; in dw_probe()
1390 dw->dma.device_tx_status = dma_chan_tx_status; in dw_probe()
1391 dw->dma.device_issue_pending = dma_chan_issue_pending; in dw_probe()
1392 dw->dma.device_terminate_all = dma_chan_terminate_all; in dw_probe()
1393 dw->dma.device_pause = dma_chan_pause; in dw_probe()
1394 dw->dma.device_resume = dma_chan_resume; in dw_probe()
1396 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources; in dw_probe()
1397 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; in dw_probe()
1399 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; in dw_probe()
1400 dw->dma.device_synchronize = dw_axi_dma_synchronize; in dw_probe()
1401 dw->dma.device_config = dw_axi_dma_chan_slave_config; in dw_probe()
1402 dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; in dw_probe()
1403 dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; in dw_probe()
1410 dw->dma.dev->dma_parms = &dw->dma_parms; in dw_probe()
1430 ret = dmaenginem_async_device_register(&dw->dma); in dw_probe()
1436 dw_axi_dma_of_xlate, dw); in dw_probe()
1442 dw->hdata->nr_channels); in dw_probe()
1455 struct dw_axi_dma *dw = chip->dw; in dw_remove() local
1463 for (i = 0; i < dw->hdata->nr_channels; i++) { in dw_remove()
1464 axi_chan_disable(&chip->dw->chan[i]); in dw_remove()
1465 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); in dw_remove()
1476 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, in dw_remove()