Lines Matching +full:0 +full:x9038
36 * Map all interfaces/rings to register index 0 in eip197_trc_cache_setupvirt()
44 for (i = 0; i < 4; i++) in eip197_trc_cache_setupvirt()
45 writel(0, priv->base + EIP197_FLUE_IFC_LUT(i)); in eip197_trc_cache_setupvirt()
51 for (i = 0; i < priv->config.rings; i++) { in eip197_trc_cache_setupvirt()
52 writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i)); in eip197_trc_cache_setupvirt()
53 writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i)); in eip197_trc_cache_setupvirt()
57 writel(0, priv->base + EIP197_FLUE_OFFSETS); in eip197_trc_cache_setupvirt()
58 writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET); in eip197_trc_cache_setupvirt()
88 addrlo = 0; in eip197_trc_cache_probe()
89 actbank = min(maxbanks - 1, 0); in eip197_trc_cache_probe()
93 marker = (addrmid ^ 0xabadbabe) & probemask; /* Unique */ in eip197_trc_cache_probe()
97 (addrmid & 0xffff)); in eip197_trc_cache_probe()
106 (addralias & 0xffff)); in eip197_trc_cache_probe()
113 (addrmid & 0xffff)); in eip197_trc_cache_probe()
132 for (i = 0; i < cs_rc_max; i++) { in eip197_trc_cache_clear()
140 if (i == 0) in eip197_trc_cache_clear()
146 writel(0, priv->base + offset + 8); in eip197_trc_cache_clear()
147 writel(0, priv->base + offset + 12); in eip197_trc_cache_clear()
152 for (i = 0; i < cs_ht_wc; i++) in eip197_trc_cache_clear()
153 writel(GENMASK(29, 0), in eip197_trc_cache_clear()
180 writel(0, priv->base + EIP197_TRC_ECCCTRL); in eip197_trc_cache_init()
191 dsize = eip197_trc_cache_probe(priv, maxbanks, 0xffffffff, 32); in eip197_trc_cache_init()
204 asize = eip197_trc_cache_probe(priv, 0, 0x3fffffff, 16) >> 4; in eip197_trc_cache_init()
207 writel(0, priv->base + EIP197_TRC_ECCCTRL); in eip197_trc_cache_init()
249 val = EIP197_TRC_FREECHAIN_HEAD_PTR(0) | in eip197_trc_cache_init()
266 return 0; in eip197_trc_cache_init()
274 for (pe = 0; pe < priv->config.pes; pe++) { in eip197_init_firmware()
277 writel(0, EIP197_PE(priv) + EIP197_PE_ICE_PPTF_CTRL(pe)); in eip197_init_firmware()
288 for (i = 0; i < EIP197_NUM_OF_SCRATCH_BLOCKS; i++) in eip197_init_firmware()
289 writel(0, EIP197_PE(priv) + in eip197_init_firmware()
323 for (i = 0; i < fw->size / sizeof(u32); i++) in eip197_write_firmware()
346 for (pe = 0; pe < priv->config.pes; pe++) { in poll_fw_ready()
369 for (pe = 0; pe < priv->config.pes; pe++) { in eip197_start_firmware()
371 writel(0, EIP197_PE(priv) + EIP197_PE_ICE_RAM_CTRL(pe)); in eip197_start_firmware()
375 val = 0; in eip197_start_firmware()
384 val = 0; in eip197_start_firmware()
399 if (!poll_fw_ready(priv, 0)) in eip197_start_firmware()
410 int i, j, ret = 0, pe; in eip197_load_firmwares()
411 int ipuesz, ifppsz, minifw = 0; in eip197_load_firmwares()
422 for (i = 0; i < FW_NB; i++) { in eip197_load_firmwares()
444 for (pe = 0; pe < priv->config.pes; pe++) in eip197_load_firmwares()
452 return 0; in eip197_load_firmwares()
458 for (j = 0; j < i; j++) in eip197_load_firmwares()
502 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_setup_cdesc_rings()
523 writel(GENMASK(5, 0), in safexcel_hw_setup_cdesc_rings()
527 return 0; in safexcel_hw_setup_cdesc_rings()
550 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_setup_rdesc_rings()
574 writel(GENMASK(7, 0), in safexcel_hw_setup_rdesc_rings()
583 return 0; in safexcel_hw_setup_rdesc_rings()
612 writel(0, EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ENABLE_CTRL); in safexcel_hw_init()
615 writel(GENMASK(31, 0), EIP197_HIA_AIC_G(priv) + EIP197_HIA_AIC_G_ACK); in safexcel_hw_init()
618 for (pe = 0; pe < priv->config.pes; pe++) { in safexcel_hw_init()
641 writel(0, EIP197_HIA_DFE_THR(priv) + EIP197_HIA_DFE_THR_CTRL(pe)); in safexcel_hw_init()
654 GENMASK(priv->config.rings - 1, 0), in safexcel_hw_init()
689 writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe)); in safexcel_hw_init()
712 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_init()
714 writel(GENMASK(31, 0), in safexcel_hw_init()
718 writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_CFG); in safexcel_hw_init()
728 writel(0, in safexcel_hw_init()
730 writel(0, in safexcel_hw_init()
738 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_init()
740 writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_CFG); in safexcel_hw_init()
750 writel(0, in safexcel_hw_init()
752 writel(0, in safexcel_hw_init()
760 for (pe = 0; pe < priv->config.pes; pe++) { in safexcel_hw_init()
762 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), in safexcel_hw_init()
766 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0), in safexcel_hw_init()
779 EIP197_PE(priv) + EIP197_PE_EIP96_TOKEN_CTRL2(0)); in safexcel_hw_init()
794 0; in safexcel_hw_init()
816 int ret, nreq = 0, cdesc = 0, rdesc = 0, commands, results; in safexcel_dequeue()
900 return 0; in safexcel_rdesc_check_errors()
908 if (result_data->error_code & 0x4066) { in safexcel_rdesc_check_errors()
916 (BIT(7) | BIT(4) | BIT(3) | BIT(0))) { in safexcel_rdesc_check_errors()
983 int ret = 0; in safexcel_invalidate_cache()
986 cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma, in safexcel_invalidate_cache()
992 cdesc->control_data.options = 0; in safexcel_invalidate_cache()
997 rdesc = safexcel_add_rdesc(priv, ring, true, true, 0, 0); in safexcel_invalidate_cache()
1019 int ret, i, nreq, ndesc, tot_descs, handled = 0; in safexcel_handle_result_descriptor()
1023 tot_descs = 0; in safexcel_handle_result_descriptor()
1031 for (i = 0; i < nreq; i++) { in safexcel_handle_result_descriptor()
1037 if (ndesc < 0) { in safexcel_handle_result_descriptor()
1117 writel(stat & 0xff, in safexcel_irq_ring()
1156 if (irq < 0) { in safexcel_request_ring_irq()
1163 char irq_name[6] = {0}; /* "ringX\0" */ in safexcel_request_ring_irq()
1169 if (irq < 0) in safexcel_request_ring_irq()
1268 int i, j, ret = 0; in safexcel_register_algorithms()
1270 for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) { in safexcel_register_algorithms()
1290 return 0; in safexcel_register_algorithms()
1293 for (j = 0; j < i; j++) { in safexcel_register_algorithms()
1315 for (i = 0; i < ARRAY_SIZE(safexcel_algs); i++) { in safexcel_unregister_algorithms()
1407 1, 0); in safexcel_probe_generic()
1418 mask = 0; /* do not swap */ in safexcel_probe_generic()
1482 version = readl(EIP197_PE(priv) + + EIP197_PE_VERSION(0)); in safexcel_probe_generic()
1490 version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0)); in safexcel_probe_generic()
1500 priv->hwconfig.icever = 0; in safexcel_probe_generic()
1501 priv->hwconfig.ocever = 0; in safexcel_probe_generic()
1502 priv->hwconfig.psever = 0; in safexcel_probe_generic()
1505 peopt = readl(EIP197_PE(priv) + EIP197_PE_OPTIONS(0)); in safexcel_probe_generic()
1525 EIP197_PE_ICE_VERSION(0)); in safexcel_probe_generic()
1536 version = readl(EIP197_PE(priv) + EIP197_PE_PSE_VERSION(0)); in safexcel_probe_generic()
1544 EIP197_PE_ICE_VERSION(0)); in safexcel_probe_generic()
1571 for (i = 0; i < EIP197_MAX_RING_AIC; i++) { in safexcel_probe_generic()
1586 EIP197_PE_EIP96_OPTIONS(0)); in safexcel_probe_generic()
1611 if (ret < 0) { in safexcel_probe_generic()
1624 for (i = 0; i < priv->config.rings; i++) { in safexcel_probe_generic()
1625 char wq_name[9] = {0}; in safexcel_probe_generic()
1658 if (irq < 0) { in safexcel_probe_generic()
1675 priv->ring[i].requests = 0; in safexcel_probe_generic()
1685 atomic_set(&priv->ring_used, 0); in safexcel_probe_generic()
1699 return 0; in safexcel_probe_generic()
1706 for (i = 0; i < priv->config.rings; i++) { in safexcel_hw_reset_rings()
1708 writel(GENMASK(5, 0), EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_STAT); in safexcel_hw_reset_rings()
1709 writel(GENMASK(7, 0), EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_STAT); in safexcel_hw_reset_rings()
1712 writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO); in safexcel_hw_reset_rings()
1713 writel(0, EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI); in safexcel_hw_reset_rings()
1716 writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_LO); in safexcel_hw_reset_rings()
1717 writel(0, EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI); in safexcel_hw_reset_rings()
1738 priv->base = devm_platform_ioremap_resource(pdev, 0); in safexcel_probe()
1777 ret = safexcel_probe_generic(pdev, priv, 0); in safexcel_probe()
1781 return 0; in safexcel_probe()
1801 for (i = 0; i < priv->config.rings; i++) { in safexcel_remove()
1806 return 0; in safexcel_remove()
1880 priv->base = pcim_iomap_table(pdev)[0]; in safexcel_pci_probe()
1895 (val & 0xff)); in safexcel_pci_probe()
1908 writel(GENMASK(31, 0), in safexcel_pci_probe()
1921 writel(0, priv->base + EIP197_XLX_GPIO_BASE); in safexcel_pci_probe()
1940 for (i = 0; i < priv->config.rings; i++) in safexcel_pci_remove()
1948 PCI_DEVICE_SUB(PCI_VENDOR_ID_XILINX, 0x9038,
1949 0x16ae, 0xc522),