Lines Matching +full:0 +full:x100008
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
30 #define QM_EQ_EVENT_IRQ_VECTOR 0
36 #define QM_MB_CMD_SQC 0x0
37 #define QM_MB_CMD_CQC 0x1
38 #define QM_MB_CMD_EQC 0x2
39 #define QM_MB_CMD_AEQC 0x3
40 #define QM_MB_CMD_SQC_BT 0x4
41 #define QM_MB_CMD_CQC_BT 0x5
42 #define QM_MB_CMD_SQC_VFT_V2 0x6
43 #define QM_MB_CMD_STOP_QP 0x8
44 #define QM_MB_CMD_SRC 0xc
45 #define QM_MB_CMD_DST 0xd
47 #define QM_MB_CMD_SEND_BASE 0x300
51 #define QM_MB_CMD_DATA_ADDR_L 0x304
52 #define QM_MB_CMD_DATA_ADDR_H 0x308
53 #define QM_MB_PING_ALL_VFS 0xffff
55 #define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
58 #define QM_SQ_HOP_NUM_SHIFT 0
62 #define QM_SQ_PRIORITY_SHIFT 0
65 #define QM_QC_PASID_ENABLE 0x1
68 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
69 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
72 #define QM_CQ_HOP_NUM_SHIFT 0
76 #define QM_CQ_PHASE_SHIFT 0
79 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
81 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
87 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
88 #define QM_EQE_CQN_MASK GENMASK(15, 0)
90 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
93 #define QM_DOORBELL_CMD_SQ 0
98 #define QM_DOORBELL_BASE_V1 0x340
102 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
103 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
104 #define QM_QUE_ISO_CFG_V 0x0030
105 #define QM_PAGE_SIZE 0x0034
106 #define QM_QUE_ISO_EN 0x100154
107 #define QM_CAPBILITY 0x100158
108 #define QM_QP_NUN_MASK GENMASK(10, 0)
109 #define QM_QP_DB_INTERVAL 0x10000
116 #define QM_MEM_START_INIT 0x100040
117 #define QM_MEM_INIT_DONE 0x100044
118 #define QM_VFT_CFG_RDY 0x10006c
119 #define QM_VFT_CFG_OP_WR 0x100058
120 #define QM_VFT_CFG_TYPE 0x10005c
121 #define QM_SQC_VFT 0x0
122 #define QM_CQC_VFT 0x1
123 #define QM_VFT_CFG 0x100060
124 #define QM_VFT_CFG_OP_ENABLE 0x100054
126 #define QM_VFT_CFG_DATA_L 0x100064
127 #define QM_VFT_CFG_DATA_H 0x100068
140 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
142 #define QM_SQC_VFT_NUM_MASK_v2 GENMASK(9, 0)
144 #define QM_DFX_CNT_CLR_CE 0x100118
146 #define QM_ABNORMAL_INT_SOURCE 0x100000
147 #define QM_ABNORMAL_INT_SOURCE_CLR GENMASK(14, 0)
148 #define QM_ABNORMAL_INT_MASK 0x100004
149 #define QM_ABNORMAL_INT_MASK_VALUE 0x7fff
150 #define QM_ABNORMAL_INT_STATUS 0x100008
151 #define QM_ABNORMAL_INT_SET 0x10000c
152 #define QM_ABNORMAL_INF00 0x100010
153 #define QM_FIFO_OVERFLOW_TYPE 0xc0
155 #define QM_FIFO_OVERFLOW_VF 0x3f
156 #define QM_ABNORMAL_INF01 0x100014
157 #define QM_DB_TIMEOUT_TYPE 0xc0
159 #define QM_DB_TIMEOUT_VF 0x3f
160 #define QM_RAS_CE_ENABLE 0x1000ec
161 #define QM_RAS_FE_ENABLE 0x1000f0
162 #define QM_RAS_NFE_ENABLE 0x1000f4
163 #define QM_RAS_CE_THRESHOLD 0x1000f8
165 #define QM_RAS_MSI_INT_SEL 0x1040f4
166 #define QM_OOO_SHUTDOWN_SEL 0x1040f8
169 #define QM_PEH_VENDOR_ID 0x1000d8
170 #define ACC_VENDOR_ID_VALUE 0x5a5a
171 #define QM_PEH_DFX_INFO0 0x1000fc
172 #define QM_PEH_DFX_INFO1 0x100100
173 #define QM_PEH_DFX_MASK (BIT(0) | BIT(2))
176 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
177 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
179 #define ACC_MASTER_TRANS_RETURN 0x300150
180 #define ACC_MASTER_GLOBAL_CTRL 0x300000
181 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
183 #define ACC_AM_ROB_ECC_INT_STS 0x300104
188 #define QM_IFC_READY_STATUS 0x100128
189 #define QM_IFC_C_STS_M 0x10012C
190 #define QM_IFC_INT_SET_P 0x100130
191 #define QM_IFC_INT_CFG 0x100134
192 #define QM_IFC_INT_SOURCE_P 0x100138
193 #define QM_IFC_INT_SOURCE_V 0x0020
194 #define QM_IFC_INT_MASK 0x0024
195 #define QM_IFC_INT_STATUS 0x0028
196 #define QM_IFC_INT_SET_V 0x002C
197 #define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
198 #define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
199 #define QM_IFC_INT_SOURCE_MASK BIT(0)
200 #define QM_IFC_INT_DISABLE BIT(0)
201 #define QM_IFC_INT_STATUS_MASK BIT(0)
202 #define QM_IFC_INT_SET_MASK BIT(0)
211 #define QM_DFX_MB_CNT_VF 0x104010
212 #define QM_DFX_DB_CNT_VF 0x104020
213 #define QM_DFX_SQE_CNT_VF_SQN 0x104030
214 #define QM_DFX_CQE_CNT_VF_CQN 0x104040
216 #define CURRENT_FUN_MASK GENMASK(5, 0)
224 #define QM_CACHE_WB_START 0x204
225 #define QM_CACHE_WB_DONE 0x208
229 #define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0)
235 #define QM_PCI_COMMAND_INVALID ~0
239 #define QM_SQE_ADDR_MASK GENMASK(7, 0)
242 #define QM_DRIVER_REMOVING 0
251 #define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)
265 #define QM_QOS_TICK 0x300U
266 #define QM_QOS_DIVISOR_CLK 0x1f40U
299 (qc)->head = 0; \
300 (qc)->tail = 0; \
303 (qc)->dw3 = 0; \
304 (qc)->w8 = 0; \
305 (qc)->rsvd0 = 0; \
307 (qc)->w11 = 0; \
308 (qc)->rsvd1 = 0; \
309 } while (0)
312 SQC_VFT = 0,
329 QM_PF_FLR_PREPARE = 0x01,
468 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
543 enum qp_state qp_curr = 0; in qm_qp_avail_state()
590 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) | in qm_mb_pre_init()
591 (0x1 << QM_MB_BUSY_SHIFT)); in qm_mb_pre_init()
595 mailbox->rsvd = 0; in qm_mb_pre_init()
598 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
605 0x1), POLL_PERIOD, POLL_TIMEOUT); in qm_wait_mb_ready()
612 unsigned long tmp0 = 0, tmp1 = 0; in qm_mb_write()
620 asm volatile("ldp %0, %1, %3\n" in qm_mb_write()
621 "stp %0, %1, %2\n" in qm_mb_write()
644 return 0; in qm_mb_nolock()
683 u16 randata = 0; in qm_db_v2()
712 writel(0x1, qm->io_base + QM_MEM_START_INIT); in qm_dev_mem_reset()
714 val & BIT(0), POLL_PERIOD, in qm_dev_mem_reset()
745 return 0; in qm_pm_get_sync()
748 if (ret < 0) { in qm_pm_get_sync()
753 return 0; in qm_pm_get_sync()
778 qp->qp_status.cq_head = 0; in qm_cq_head_update()
804 qp->qp_status.cq_head, 0); in qm_poll_qp()
819 int eqe_num = 0; in qm_work_process()
829 qm->status.eq_head = 0; in qm_work_process()
836 eqe_num = 0; in qm_work_process()
837 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_work_process()
841 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_work_process()
866 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_irq()
908 qm->status.aeq_head = 0; in qm_aeq_irq()
914 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_aeq_irq()
942 qp_status->sq_tail = 0; in qm_init_qp_status()
943 qp_status->cq_head = 0; in qm_init_qp_status()
945 atomic_set(&qp_status->used, 0); in qm_init_qp_status()
951 u32 page_type = 0x0; in qm_init_prefetch()
958 page_type = 0x0; in qm_init_prefetch()
961 page_type = 0x1; in qm_init_prefetch()
964 page_type = 0x2; in qm_init_prefetch()
992 if (ir < typical_qos_val[0]) in acc_shaper_calc_cbs_s()
1011 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) { in qm_get_shaper_para()
1012 for (cir_s = 0; cir_s <= QM_QOS_MAX_CIR_S; cir_s++) { in qm_get_shaper_para()
1026 return 0; in qm_get_shaper_para()
1038 u64 tmp = 0; in qm_vft_data_cfg()
1040 if (number > 0) { in qm_vft_data_cfg()
1089 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1094 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR); in qm_set_vft_common()
1103 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_set_vft_common()
1104 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_set_vft_common()
1107 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1129 return 0; in qm_shaper_init_vft()
1151 return 0; in qm_set_sqc_cqc_vft()
1154 ret = qm_set_vft_common(qm, i, fun_num, 0, 0); in qm_set_sqc_cqc_vft()
1166 ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); in qm_get_vft_v2()
1176 return 0; in qm_get_vft_v2()
1226 return 0; in current_q_write()
1234 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
1242 return 0; in clear_enable_write()
1274 return 0; in current_qm_write()
1327 if (*pos != 0) in qm_debug_write()
1328 return 0; in qm_debug_write()
1335 if (len < 0) in qm_debug_write()
1338 tbuf[len] = '\0'; in qm_debug_write()
1339 if (kstrtoul(tbuf, 0, &val)) in qm_debug_write()
1380 {"QM_ECC_1BIT_CNT ", 0x104000ull},
1381 {"QM_ECC_MBIT_CNT ", 0x104008ull},
1382 {"QM_DFX_MB_CNT ", 0x104018ull},
1383 {"QM_DFX_DB_CNT ", 0x104028ull},
1384 {"QM_DFX_SQE_CNT ", 0x104038ull},
1385 {"QM_DFX_CQE_CNT ", 0x104048ull},
1386 {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull},
1387 {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull},
1388 {"QM_DFX_ACC_FINISH_CNT ", 0x104060ull},
1389 {"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull},
1390 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1391 {"QM_ECC_1BIT_INF ", 0x104004ull},
1392 {"QM_ECC_MBIT_INF ", 0x10400cull},
1393 {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull},
1394 {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull},
1395 {"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull},
1396 {"QM_DFX_FF_ST0 ", 0x1040c8ull},
1397 {"QM_DFX_FF_ST1 ", 0x1040ccull},
1398 {"QM_DFX_FF_ST2 ", 0x1040d0ull},
1399 {"QM_DFX_FF_ST3 ", 0x1040d4ull},
1400 {"QM_DFX_FF_ST4 ", 0x1040d8ull},
1401 {"QM_DFX_FF_ST5 ", 0x1040dcull},
1402 {"QM_DFX_FF_ST6 ", 0x1040e0ull},
1403 {"QM_IN_IDLE_ST ", 0x1040e4ull},
1407 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1430 for (i = 0; i < regs_len; i++) { in hisi_qm_regs_dump()
1432 seq_printf(s, "%s= 0x%08x\n", regs[i].name, val); in hisi_qm_regs_dump()
1457 return 0; in qm_regs_show()
1515 for (i = 0; i < info_size; i++, info_curr++) { in dump_show()
1516 if (i % BYTE_PER_DW == 0) in dump_show()
1527 for (i = 0; i < info_size; i += BYTE_PER_DW) { in dump_show()
1535 return 0; in dump_show()
1559 ret = kstrtou32(s, 0, &qp_id); in qm_sqc_dump()
1561 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_sqc_dump()
1605 ret = kstrtou32(s, 0, &qp_id); in qm_cqc_dump()
1607 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1); in qm_cqc_dump()
1657 ret = qm_mb(qm, cmd, xeqc_dma, 0, 1); in qm_eqc_aeqc_dump()
1684 ret = kstrtou32(presult, 0, q_id); in q_dump_param_parse()
1686 dev_err(dev, "Please input qp num (0-%u)", qp_num - 1); in q_dump_param_parse()
1696 ret = kstrtou32(presult, 0, e_id); in q_dump_param_parse()
1698 dev_err(dev, "Please input sqe num (0-%d)", QM_Q_DEPTH - 1); in q_dump_param_parse()
1707 return 0; in q_dump_param_parse()
1773 ret = kstrtou32(s, 0, &xeqe_id); in qm_eq_aeq_dump()
1778 dev_err(dev, "Please input eqe num (0-%d)", QM_EQ_DEPTH - 1); in qm_eq_aeq_dump()
1781 dev_err(dev, "Please input aeqe num (0-%d)", QM_Q_DEPTH - 1); in qm_eq_aeq_dump()
1824 return 0; in qm_dbg_help()
1884 return 0; in qm_cmd_write()
1892 return 0; in qm_cmd_write()
1907 *cmd_buf_tmp = '\0'; in qm_cmd_write()
2000 writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL); in qm_hw_error_uninit_v3()
2010 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) { in qm_log_hw_error()
2015 dev_err(dev, "%s [error status=0x%x] found\n", in qm_log_hw_error()
2085 return 0; in qm_check_dev_error()
2103 qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0); in qm_get_mb_cmd()
2163 int cnt = 0; in qm_wait_vf_prepare_finish()
2164 int ret = 0; in qm_wait_vf_prepare_finish()
2169 return 0; in qm_wait_vf_prepare_finish()
2226 int cnt = 0; in qm_ping_single_vf()
2230 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, fun_num, 0); in qm_ping_single_vf()
2263 u64 val = 0; in qm_ping_all_vfs()
2264 int cnt = 0; in qm_ping_all_vfs()
2268 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, QM_MB_PING_ALL_VFS, 0); in qm_ping_all_vfs()
2285 return 0; in qm_ping_all_vfs()
2306 int cnt = 0; in qm_ping_pf()
2310 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, 0, 0); in qm_ping_pf()
2339 return qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0); in qm_stop_qp()
2348 0); in qm_set_msi()
2354 return 0; in qm_set_msi()
2361 return 0; in qm_set_msi()
2367 u32 cmd = ~0; in qm_wait_msi_finish()
2368 int cnt = 0; in qm_wait_msi_finish()
2413 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_msi_v3()
2416 return 0; in qm_set_msi_v3()
2423 ret = 0; in qm_set_msi_v3()
2486 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC); in qm_create_qp_nolock()
2487 if (qp_id < 0) { in qm_create_qp_nolock()
2496 memset(qp->cqe, 0, sizeof(struct qm_cqe) * QM_Q_DEPTH); in qm_create_qp_nolock()
2578 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size)); in qm_sq_ctx_cfg()
2582 sqc->w8 = 0; /* rand_qc */ in qm_sq_ctx_cfg()
2585 sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type)); in qm_sq_ctx_cfg()
2598 ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0); in qm_sq_ctx_cfg()
2620 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, in qm_cq_ctx_cfg()
2625 cqc->w8 = 0; /* rand_qc */ in qm_cq_ctx_cfg()
2639 ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0); in qm_cq_ctx_cfg()
2677 return 0; in qm_start_qp_nolock()
2685 * After this function, qp can receive request from user. Return 0 if
2716 for (i = 0; i < qp_used; i++) { in qp_stop_fail_cb()
2738 int ret = 0, i = 0; in qm_drain_qp()
2743 return 0; in qm_drain_qp()
2806 return 0; in qm_stop_qp_nolock()
2828 return 0; in qm_stop_qp_nolock()
2835 * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
2862 * done function should clear used sqe to 0.
2883 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0); in hisi_qp_send()
2887 return 0; in hisi_qp_send()
2898 writel(0x1, qm->io_base + QM_CACHE_WB_START); in hisi_qm_cache_wb()
2900 val, val & BIT(0), POLL_PERIOD, in hisi_qm_cache_wb()
2921 u8 alg_type = 0; in hisi_qm_uacce_get_queue()
2934 return 0; in hisi_qm_uacce_get_queue()
2984 * dma_mmap_coherent() requires vm_pgoff as 0 in hisi_qm_uacce_mmap()
2988 vma->vm_pgoff = 0; in hisi_qm_uacce_mmap()
3015 int updated = 0; in hisi_qm_is_q_updated()
3049 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1) in hisi_qm_uacce_ioctl()
3062 return 0; in hisi_qm_uacce_ioctl()
3090 if (ret < 0) in qm_alloc_uacce()
3133 return 0; in qm_alloc_uacce()
3146 return 0; in qm_frozen()
3154 return 0; in qm_frozen()
3167 int ret = 0; in qm_try_frozen_vfs()
3238 for (i = num - 1; i >= 0; i--) { in hisi_qp_memory_uninit()
3266 return 0; in hisi_qp_memory_init()
3283 qm->qp_in_used = 0; in hisi_qm_pre_init()
3413 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3415 * (VF function number 0x2)
3433 status->eq_head = 0; in qm_init_eq_aeq_status()
3434 status->aeq_head = 0; in qm_init_eq_aeq_status()
3463 ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0); in qm_eq_ctx_cfg()
3492 ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0); in qm_aeq_ctx_cfg()
3526 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num); in __hisi_qm_start()
3535 ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); in __hisi_qm_start()
3539 ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); in __hisi_qm_start()
3545 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK); in __hisi_qm_start()
3546 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK); in __hisi_qm_start()
3548 return 0; in __hisi_qm_start()
3560 int ret = 0; in hisi_qm_start()
3572 dev_err(dev, "qp_num should not be 0\n"); in hisi_qm_start()
3594 if (ret < 0) in qm_restart()
3598 for (i = 0; i < qm->qp_num; i++) { in qm_restart()
3602 ret = qm_start_qp_nolock(qp, 0); in qm_restart()
3603 if (ret < 0) { in qm_restart()
3614 return 0; in qm_restart()
3624 for (i = 0; i < qm->qp_num; i++) { in qm_stop_started_qp()
3629 if (ret < 0) { in qm_stop_started_qp()
3636 return 0; in qm_stop_started_qp()
3652 for (i = 0; i < qm->qp_num; i++) { in qm_clear_queues()
3655 memset(qp->qdma.va, 0, qp->qdma.size); in qm_clear_queues()
3658 memset(qm->qdma.va, 0, qm->qdma.size); in qm_clear_queues()
3673 int ret = 0; in hisi_qm_stop()
3686 if (ret < 0) { in hisi_qm_stop()
3693 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK); in hisi_qm_stop()
3694 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK); in hisi_qm_stop()
3697 ret = hisi_qm_set_vft(qm, 0, 0, 0); in hisi_qm_stop()
3698 if (ret < 0) { in hisi_qm_stop()
3738 atomic64_set((atomic64_t *)data, 0); in qm_debugfs_atomic64_set()
3740 return 0; in qm_debugfs_atomic64_set()
3747 return 0; in qm_debugfs_atomic64_get()
3836 if (!qps || qp_num <= 0) in hisi_qm_free_qps()
3839 for (i = qp_num - 1; i >= 0; i--) in hisi_qm_free_qps()
3861 int dev_node = 0; in hisi_qm_sort_devices()
3868 if (dev_node < 0) in hisi_qm_sort_devices()
3869 dev_node = 0; in hisi_qm_sort_devices()
3888 return 0; in hisi_qm_sort_devices()
3911 if (!qps || !qm_list || qp_num <= 0) in hisi_qm_alloc_qps_node()
3921 for (i = 0; i < qp_num; i++) { in hisi_qm_alloc_qps_node()
3930 ret = 0; in hisi_qm_alloc_qps_node()
3965 for (i = num_vfs; i > 0; i--) { in qm_vf_q_assign()
3972 remain_q_num = 0; in qm_vf_q_assign()
3973 } else if (remain_q_num > 0) { in qm_vf_q_assign()
3984 hisi_qm_set_vft(qm, j, 0, 0); in qm_vf_q_assign()
3990 return 0; in qm_vf_q_assign()
3999 ret = hisi_qm_set_vft(qm, i, 0, 0); in qm_clear_vft_config()
4003 qm->vfs_num = 0; in qm_clear_vft_config()
4005 return 0; in qm_clear_vft_config()
4035 return 0; in qm_func_shaper_enable()
4040 u64 cir_u = 0, cir_b = 0, cir_s = 0; in qm_get_shaper_vft_qos()
4047 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
4050 return 0; in qm_get_shaper_vft_qos()
4052 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR); in qm_get_shaper_vft_qos()
4056 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_get_shaper_vft_qos()
4057 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_get_shaper_vft_qos()
4060 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
4063 return 0; in qm_get_shaper_vft_qos()
4082 return 0; in qm_get_shaper_vft_qos()
4109 int cnt = 0; in qm_vf_read_qos()
4113 qm->mb_qos = 0; in qm_vf_read_qos()
4158 ir = qm_get_shaper_vft_qos(qm, 0); in qm_algqos_read()
4183 for (i = 0; i < buflen; i++) { in qm_qos_value_init()
4192 return 0; in qm_qos_value_init()
4201 char tbuf_bdf[QM_DBG_READ_LEN] = {0}; in qm_algqos_write()
4202 char val_buf[QM_QOS_VAL_MAX_LEN] = {0}; in qm_algqos_write()
4204 unsigned long val = 0; in qm_algqos_write()
4216 if (*pos != 0) { in qm_algqos_write()
4217 ret = 0; in qm_algqos_write()
4227 if (len < 0) { in qm_algqos_write()
4232 tbuf[len] = '\0'; in qm_algqos_write()
4240 if (val == 0 || val > QM_QOS_MAX_VAL || ret) { in qm_algqos_write()
4329 for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) { in hisi_qm_debug_init()
4353 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); in hisi_qm_debug_regs_clear()
4354 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); in hisi_qm_debug_regs_clear()
4357 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); in hisi_qm_debug_regs_clear()
4358 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); in hisi_qm_debug_regs_clear()
4364 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE); in hisi_qm_debug_regs_clear()
4367 for (i = 0; i < CNT_CYC_REGS_NUM; i++) { in hisi_qm_debug_regs_clear()
4373 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE); in hisi_qm_debug_regs_clear()
4455 memset(qm->factor + 1, 0, sizeof(struct qm_shaper_factor) * total_vfs); in hisi_qm_sriov_disable()
4462 return 0; in hisi_qm_sriov_disable()
4471 * Enable SR-IOV according to num_vfs, 0 means disable.
4475 if (num_vfs == 0) in hisi_qm_sriov_configure()
4567 return 0; in qm_check_req_recv()
4601 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_pf_mse()
4604 return 0; in qm_set_pf_mse()
4627 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_vf_mse()
4631 return 0; in qm_set_vf_mse()
4646 int ret = 0; in qm_vf_reset_prepare()
4676 return 0; in qm_try_stop_vfs()
4694 int delay = 0; in qm_wait_reset_finish()
4703 return 0; in qm_wait_reset_finish()
4764 return 0; in qm_controller_reset_prepare()
4769 u32 nfe_enb = 0; in qm_dev_ecc_mbit_handle()
4844 unsigned long long value = 0; in qm_soft_reset()
4864 return 0; in qm_soft_reset()
4873 int ret = 0; in qm_vf_reset_done()
4902 return 0; in qm_try_start_vfs()
5036 return 0; in qm_controller_reset_done()
5067 return 0; in qm_controller_reset()
5102 u32 delay = 0; in hisi_qm_reset_prepare()
5222 qm_irq, 0, qm->dev_name, qm); in qm_irq_register()
5228 qm_aeq_irq, 0, qm->dev_name, qm); in qm_irq_register()
5235 qm_abnormal_irq, 0, qm->dev_name, qm); in qm_irq_register()
5243 qm_mb_cmd_irq, 0, qm->dev_name, qm); in qm_irq_register()
5248 return 0; in qm_irq_register()
5355 val == BIT(0), QM_VF_RESET_WAIT_US, in qm_wait_pf_reset_finish()
5367 ret = qm_get_mb_cmd(qm, &msg, 0); in qm_wait_pf_reset_finish()
5368 qm_clear_cmd_interrupt(qm, 0); in qm_wait_pf_reset_finish()
5470 qm_handle_cmd_msg(qm, 0); in qm_cmd_process()
5484 int flag = 0; in hisi_qm_alg_register()
5485 int ret = 0; in hisi_qm_alg_register()
5495 return 0; in hisi_qm_alg_register()
5557 return 0; in qm_get_qp_num()
5567 if (ret < 0) { in qm_get_pci_res()
5582 QM_QUE_ISO_EN) & BIT(0); in qm_get_pci_res()
5585 QM_QUE_ISO_CFG_V) & BIT(0); in qm_get_pci_res()
5600 qm->db_interval = 0; in qm_get_pci_res()
5609 return 0; in qm_get_pci_res()
5629 if (ret < 0) { in hisi_qm_pci_init()
5639 if (ret < 0) in hisi_qm_pci_init()
5649 if (ret < 0) { in hisi_qm_pci_init()
5654 return 0; in hisi_qm_pci_init()
5687 for (i = 0; i < qm->qp_num; i++) { in hisi_qp_alloc_memory()
5695 return 0; in hisi_qp_alloc_memory()
5706 size_t off = 0; in hisi_qm_memory_init()
5717 } while (0) in hisi_qm_memory_init()
5741 return 0; in hisi_qm_memory_init()
5781 if (ret < 0) in hisi_qm_init()
5792 return 0; in hisi_qm_init()
5934 return 0; in qm_rebuild_for_resume()
5989 return 0; in hisi_qm_resume()