513 				 unsigned int *seq_size)  in cc_setup_readiv_desc()  argument
533 		hw_desc_init(&desc[*seq_size]);  in cc_setup_readiv_desc()
534 		set_dout_dlli(&desc[*seq_size], iv_dma_addr, ivsize, NS_BIT, 1);  in cc_setup_readiv_desc()
535 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_readiv_desc()
536 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_readiv_desc()
537 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_readiv_desc()
540 			set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);  in cc_setup_readiv_desc()
542 			set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE0);  in cc_setup_readiv_desc()
544 		set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_readiv_desc()
545 		(*seq_size)++;  in cc_setup_readiv_desc()
550 		hw_desc_init(&desc[*seq_size]);  in cc_setup_readiv_desc()
551 		set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);  in cc_setup_readiv_desc()
552 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_readiv_desc()
553 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_readiv_desc()
554 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_readiv_desc()
555 		set_dout_dlli(&desc[*seq_size], iv_dma_addr, CC_AES_BLOCK_SIZE,  in cc_setup_readiv_desc()
557 		set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_readiv_desc()
558 		(*seq_size)++;  in cc_setup_readiv_desc()
570 				 unsigned int *seq_size)  in cc_setup_state_desc()  argument
587 		hw_desc_init(&desc[*seq_size]);  in cc_setup_state_desc()
588 		set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,  in cc_setup_state_desc()
590 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_state_desc()
591 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_state_desc()
592 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_state_desc()
595 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);  in cc_setup_state_desc()
597 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);  in cc_setup_state_desc()
599 		(*seq_size)++;  in cc_setup_state_desc()
614 				 unsigned int *seq_size)  in cc_setup_xex_state_desc()  argument
641 		hw_desc_init(&desc[*seq_size]);  in cc_setup_xex_state_desc()
642 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_xex_state_desc()
643 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_xex_state_desc()
645 			set_hw_crypto_key(&desc[*seq_size],  in cc_setup_xex_state_desc()
648 			set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_xex_state_desc()
652 		set_xex_data_unit_size(&desc[*seq_size], nbytes);  in cc_setup_xex_state_desc()
653 		set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);  in cc_setup_xex_state_desc()
654 		set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_xex_state_desc()
655 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);  in cc_setup_xex_state_desc()
656 		(*seq_size)++;  in cc_setup_xex_state_desc()
659 		hw_desc_init(&desc[*seq_size]);  in cc_setup_xex_state_desc()
660 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);  in cc_setup_xex_state_desc()
661 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_xex_state_desc()
662 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_xex_state_desc()
663 		set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_xex_state_desc()
664 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_xex_state_desc()
665 		set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,  in cc_setup_xex_state_desc()
667 		(*seq_size)++;  in cc_setup_xex_state_desc()
691 			      unsigned int *seq_size)  in cc_setup_key_desc()  argument
709 		hw_desc_init(&desc[*seq_size]);  in cc_setup_key_desc()
710 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_key_desc()
711 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_key_desc()
715 			set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_key_desc()
716 			set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);  in cc_setup_key_desc()
721 					set_hw_crypto_key(&desc[*seq_size],  in cc_setup_key_desc()
731 					set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_key_desc()
735 				set_key_size_aes(&desc[*seq_size], key_len);  in cc_setup_key_desc()
738 				set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_key_desc()
740 				set_key_size_des(&desc[*seq_size], key_len);  in cc_setup_key_desc()
742 			set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);  in cc_setup_key_desc()
744 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_key_desc()
745 		(*seq_size)++;  in cc_setup_key_desc()
750 		hw_desc_init(&desc[*seq_size]);  in cc_setup_key_desc()
751 		set_cipher_mode(&desc[*seq_size], cipher_mode);  in cc_setup_key_desc()
752 		set_cipher_config0(&desc[*seq_size], direction);  in cc_setup_key_desc()
754 			set_hw_crypto_key(&desc[*seq_size],  in cc_setup_key_desc()
757 			set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,  in cc_setup_key_desc()
760 		set_key_size_aes(&desc[*seq_size], (key_len / 2));  in cc_setup_key_desc()
761 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_key_desc()
762 		set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);  in cc_setup_key_desc()
763 		(*seq_size)++;  in cc_setup_key_desc()
774 			       struct cc_hw_desc desc[], unsigned int *seq_size)  in cc_setup_mlli_desc()  argument
785 		hw_desc_init(&desc[*seq_size]);  in cc_setup_mlli_desc()
786 		set_din_type(&desc[*seq_size], DMA_DLLI,  in cc_setup_mlli_desc()
789 		set_dout_sram(&desc[*seq_size],  in cc_setup_mlli_desc()
792 		set_flow_mode(&desc[*seq_size], BYPASS);  in cc_setup_mlli_desc()
793 		(*seq_size)++;  in cc_setup_mlli_desc()
801 			       unsigned int *seq_size)  in cc_setup_flow_desc()  argument
815 		hw_desc_init(&desc[*seq_size]);  in cc_setup_flow_desc()
816 		set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),  in cc_setup_flow_desc()
818 		set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),  in cc_setup_flow_desc()
821 			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_flow_desc()
823 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_flow_desc()
824 		(*seq_size)++;  in cc_setup_flow_desc()
826 		hw_desc_init(&desc[*seq_size]);  in cc_setup_flow_desc()
827 		set_din_type(&desc[*seq_size], DMA_MLLI,  in cc_setup_flow_desc()
834 			set_dout_mlli(&desc[*seq_size],  in cc_setup_flow_desc()
843 			set_dout_mlli(&desc[*seq_size],  in cc_setup_flow_desc()
851 			set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);  in cc_setup_flow_desc()
853 		set_flow_mode(&desc[*seq_size], flow_mode);  in cc_setup_flow_desc()
854 		(*seq_size)++;  in cc_setup_flow_desc()