Lines Matching +full:imx8mm +full:- +full:soc
1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019 NXP
44 /* INIT RNG in non-test mode */ in build_instantiation_desc()
83 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
85 * @ctrldev - pointer to device
86 * @status - descriptor status, after being run
88 * Return: - 0 if no error occurred
89 * - -ENODEV if the DECO couldn't be acquired
90 * - -EAGAIN if an error occurred while executing the descriptor
96 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; in run_descriptor_deco0()
97 struct caam_deco __iomem *deco = ctrlpriv->deco; in run_descriptor_deco0()
103 if (ctrlpriv->virt_en == 1 || in run_descriptor_deco0()
109 of_machine_is_compatible("fsl,imx8mm") || in run_descriptor_deco0()
112 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); in run_descriptor_deco0()
114 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && in run_descriptor_deco0()
115 --timeout) in run_descriptor_deco0()
121 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); in run_descriptor_deco0()
123 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && in run_descriptor_deco0()
124 --timeout) in run_descriptor_deco0()
129 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); in run_descriptor_deco0()
130 return -ENODEV; in run_descriptor_deco0()
134 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); in run_descriptor_deco0()
145 clrsetbits_32(&deco->jr_ctl_hi, 0, flags); in run_descriptor_deco0()
149 deco_dbg_reg = rd_reg32(&deco->desc_dbg); in run_descriptor_deco0()
151 if (ctrlpriv->era < 10) in run_descriptor_deco0()
155 deco_state = (rd_reg32(&deco->dbg_exec) & in run_descriptor_deco0()
167 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); in run_descriptor_deco0()
169 *status = rd_reg32(&deco->op_status_hi) & in run_descriptor_deco0()
172 if (ctrlpriv->virt_en == 1) in run_descriptor_deco0()
173 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); in run_descriptor_deco0()
176 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); in run_descriptor_deco0()
179 return -EAGAIN; in run_descriptor_deco0()
185 * deinstantiate_rng - builds and executes a descriptor on DECO0,
187 * @ctrldev - pointer to device
188 * @state_handle_mask - bitmask containing the instantiation status
192 * Return: - 0 if no error occurred
193 * - -ENOMEM if there isn't enough memory to allocate the descriptor
194 * - -ENODEV if DECO0 couldn't be acquired
195 * - -EAGAIN if an error occurred when executing the descriptor
204 return -ENOMEM; in deinstantiate_rng()
244 * De-initialize RNG state handles initialized by this driver. in devm_deinstantiate_rng()
247 if (ctrlpriv->rng4_sh_init) in devm_deinstantiate_rng()
248 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); in devm_deinstantiate_rng()
252 * instantiate_rng - builds and executes a descriptor on DECO0,
254 * @ctrldev - pointer to device
255 * @state_handle_mask - bitmask containing the instantiation status
259 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
263 * Return: - 0 if no error occurred
264 * - -ENOMEM if there isn't enough memory to allocate the descriptor
265 * - -ENODEV if DECO0 couldn't be acquired
266 * - -EAGAIN if an error occurred when executing the descriptor
278 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; in instantiate_rng()
281 return -ENOMEM; in instantiate_rng()
322 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK; in instantiate_rng()
325 ret = -EAGAIN; in instantiate_rng()
343 * kick_trng - sets the various parameters for enabling the initialization
345 * @pdev - pointer to the platform device
346 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
350 struct device *ctrldev = &pdev->dev; in kick_trng()
356 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; in kick_trng()
357 r4tst = &ctrl->r4tst[0]; in kick_trng()
362 * force re-generation. in kick_trng()
364 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC); in kick_trng()
367 * Performance-wise, it does not make sense to in kick_trng()
374 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) in kick_trng()
379 val = rd_reg32(&r4tst->rtsdctl); in kick_trng()
382 wr_reg32(&r4tst->rtsdctl, val); in kick_trng()
384 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); in kick_trng()
386 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); in kick_trng()
388 val = rd_reg32(&r4tst->rtmctl); in kick_trng()
394 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC, in kick_trng()
424 ccbvid = rd_reg32(&ctrl->perfmon.ccb_id); in caam_get_era_from_hw()
426 if (era) /* This is '0' prior to CAAM ERA-6 */ in caam_get_era_from_hw()
429 id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms); in caam_get_era_from_hw()
437 return -ENOTSUPP; in caam_get_era_from_hw()
441 * caam_get_era() - Return the ERA of the SEC on SoC, based
442 * on "sec-era" optional property in the DTS. This property is updated
443 * by u-boot.
455 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); in caam_get_era()
456 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop); in caam_get_era()
485 .compatible = "fsl,sec-v4.0",
555 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks); in disable_clocks()
563 ctrlpriv->num_clks = data->num_clks; in init_clocks()
564 ctrlpriv->clks = devm_kmemdup(dev, data->clks, in init_clocks()
565 data->num_clks * sizeof(data->clks[0]), in init_clocks()
567 if (!ctrlpriv->clks) in init_clocks()
568 return -ENOMEM; in init_clocks()
570 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks); in init_clocks()
577 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks); in init_clocks()
596 if (mc_version->major > major) in check_version()
599 if (mc_version->major == major) { in check_version()
600 if (mc_version->minor > minor) in check_version()
603 if (mc_version->minor == minor && in check_version()
604 mc_version->revision > revision) in check_version()
629 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL); in caam_probe()
631 return -ENOMEM; in caam_probe()
633 dev = &pdev->dev; in caam_probe()
635 nprop = pdev->dev.of_node; in caam_probe()
641 if (!imx_soc_match->data) { in caam_probe()
642 dev_err(dev, "No clock data provided for i.MX SoC"); in caam_probe()
643 return -EINVAL; in caam_probe()
646 ret = init_clocks(dev, imx_soc_match->data); in caam_probe()
661 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) & in caam_probe()
663 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); in caam_probe()
664 if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR) in caam_probe()
669 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK); in caam_probe()
673 if (ctrlpriv->qi_present && !caam_dpaa2) { in caam_probe()
676 return -EPROBE_DEFER; in caam_probe()
679 return -ENODEV; in caam_probe()
684 return -EPROBE_DEFER; in caam_probe()
687 return -ENODEV; in caam_probe()
701 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl; in caam_probe()
702 ctrlpriv->assure = (struct caam_assurance __iomem __force *) in caam_probe()
706 ctrlpriv->deco = (struct caam_deco __iomem __force *) in caam_probe()
712 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); in caam_probe()
713 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc"); in caam_probe()
714 ctrlpriv->mc_en = !!np; in caam_probe()
718 if (ctrlpriv->mc_en) { in caam_probe()
725 return -EPROBE_DEFER; in caam_probe()
735 if (!ctrlpriv->mc_en) in caam_probe()
736 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, in caam_probe()
740 handle_imx6_err005766(&ctrl->mcr); in caam_probe()
746 scfgr = rd_reg32(&ctrl->scfgr); in caam_probe()
748 ctrlpriv->virt_en = 0; in caam_probe()
756 ctrlpriv->virt_en = 1; in caam_probe()
760 ctrlpriv->virt_en = 1; in caam_probe()
763 if (ctrlpriv->virt_en == 1) in caam_probe()
764 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START | in caam_probe()
774 ctrlpriv->era = caam_get_era(ctrl); in caam_probe()
775 ctrlpriv->domain = iommu_get_domain_for_dev(dev); in caam_probe()
788 if (ctrlpriv->qi_present && !caam_dpaa2) { in caam_probe()
789 ctrlpriv->qi = (struct caam_queue_if __iomem __force *) in caam_probe()
794 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); in caam_probe()
796 /* If QMAN driver is present, init CAAM-QI backend */ in caam_probe()
806 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || in caam_probe()
807 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { in caam_probe()
808 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *) in caam_probe()
813 ctrlpriv->total_jobrs++; in caam_probe()
818 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) { in caam_probe()
820 return -ENOMEM; in caam_probe()
823 if (ctrlpriv->era < 10) in caam_probe()
824 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) & in caam_probe()
827 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >> in caam_probe()
835 if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) { in caam_probe()
836 ctrlpriv->rng4_sh_init = in caam_probe()
837 rd_reg32(&ctrl->r4tst[0].rdsta); in caam_probe()
844 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; in caam_probe()
845 ctrlpriv->rng4_sh_init &= RDSTA_MASK; in caam_probe()
848 rd_reg32(&ctrl->r4tst[0].rdsta) & in caam_probe()
852 * (e.g. u-boot) then it is assumed that the entropy in caam_probe()
858 if (!(ctrlpriv->rng4_sh_init || inst_handles)) { in caam_probe()
874 if (ret == -EAGAIN) in caam_probe()
880 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); in caam_probe()
889 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK; in caam_probe()
892 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE); in caam_probe()
897 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | in caam_probe()
898 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); in caam_probe()
902 ctrlpriv->era); in caam_probe()
904 ctrlpriv->total_jobrs, ctrlpriv->qi_present); in caam_probe()
925 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");