Lines Matching +full:zynqmp +full:- +full:aes
1 # SPDX-License-Identifier: GPL-2.0-only
29 tristate "PadLock driver for AES algorithm"
34 Use VIA PadLock for AES algorithm.
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
62 engine for the CryptoAPI AES algorithm.
65 will be called geode-aes.
131 AES cipher algorithms for use with protected key.
142 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
152 SHA256 secure hash standard (DFIPS 180-2).
194 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
200 tristate "AES cipher algorithms"
206 AES cipher algorithms (FIPS-197).
211 for all AES key sizes.
212 As of z196 the CTR mode is hardware accelerated for all AES
223 and uses triple-DES to generate secure random numbers like the
224 ANSI X9.17 standard. User-space programs access the
225 pseudo-random-number device through the char device /dev/prandom.
240 tristate "CRC-32 algorithms"
247 can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
248 and CRC-32C (Castagnoli).
264 sub-units. One set provides the Modular Arithmetic Unit,
380 This option provides the kernel-side support for the TRNG hardware
406 tristate "Support for OMAP AES hw engine"
416 OMAP processors have AES module accelerator. Select this if you
417 want to use the OMAP module for AES algorithms.
449 This driver provides kernel-side support through the
454 module will be called exynos-rng.
466 Select this to offload Samsung S5PV210 or S5PC110, Exynos from AES
479 needed for small and zero-size messages.
497 tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
500 Driver for ST-Ericsson UX500 crypto engine.
511 Some Atmel processors can combine the AES and SHA hw accelerators
517 tristate "Support for Atmel AES hw accelerator"
525 Some Atmel processors have AES hw accelerator.
527 AES algorithms.
530 will be called atmel-aes.
543 will be called atmel-tdes.
556 will be called atmel-sha.
574 will be called atmel-ecc.
589 will be called atmel-sha204a.
613 co-processor on the die.
616 will be called mxs-dcp.
668 (default), hashes-only, or skciphers-only.
671 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
675 algorithms, sharing the load with the CPU. Enabling skciphers-only
685 - AES (CBC, CTR, ECB, XTS)
686 - 3DES (CBC, ECB)
687 - DES (CBC, ECB)
688 - SHA1, HMAC-SHA1
689 - SHA256, HMAC-SHA256
692 bool "Symmetric-key ciphers only"
695 Enable symmetric-key ciphers only:
696 - AES (CBC, CTR, ECB, XTS)
697 - 3DES (ECB, CBC)
698 - DES (ECB, CBC)
705 - SHA1, HMAC-SHA1
706 - SHA256, HMAC-SHA256
713 - authenc()
714 - ccm(aes)
715 - rfc4309(ccm(aes))
719 int "Default maximum request size to use software for AES"
723 This sets the default maximum request size to perform AES requests
728 Considering the 256-bit ciphers, software is 2-3 times faster than
729 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
730 With 128-bit keys, the break-even point would be around 1024-bytes.
733 cost in CPU usage. The minimum recommended setting is 16-bytes
734 (1 AES block), since AES-GCM will fail if you set it lower.
737 Note that 192-bit keys are not supported by the hardware and are
750 module will be called qcom-rng. If unsure, say N.
785 Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
788 tristate "Support for Xilinx ZynqMP AES hw accelerator"
794 Xilinx ZynqMP has AES-GCM engine used for symmetric key
795 encryption and decryption. This driver interfaces with AES hw
796 accelerator. Select this if you want to use the ZynqMP module
797 for AES algorithms.
837 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
839 AES block ciphers in ECB and CBC mode, as well as SHA1, SHA224, SHA256,
841 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
844 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
857 Enables the driver for the on-chip crypto accelerator