Lines Matching +full:secure +full:- +full:only
1 # SPDX-License-Identifier: GPL-2.0-only
25 The instructions are used only when the CPU supports them.
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
118 Please note that creation of protected keys from secure keys
142 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
152 SHA256 secure hash standard (DFIPS 180-2).
162 SHA512 secure hash standard.
172 SHA3_256 secure hash standard.
182 SHA3_512 secure hash standard.
194 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
206 AES cipher algorithms (FIPS-197).
223 and uses triple-DES to generate secure random numbers like the
224 ANSI X9.17 standard. User-space programs access the
225 pseudo-random-number device through the char device /dev/prandom.
240 tristate "CRC-32 algorithms"
247 can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
248 and CRC-32C (Castagnoli).
264 sub-units. One set provides the Modular Arithmetic Unit,
380 This option provides the kernel-side support for the TRNG hardware
449 This driver provides kernel-side support through the
454 module will be called exynos-rng.
479 needed for small and zero-size messages.
489 does not actually enable any drivers, it only allows you to select
497 tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
500 Driver for ST-Ericsson UX500 crypto engine.
530 will be called atmel-aes.
543 will be called atmel-tdes.
556 will be called atmel-sha.
574 will be called atmel-ecc.
589 will be called atmel-sha204a.
592 bool "Support for AMD Secure Processor"
595 The AMD Secure Processor provides support for the Cryptographic Coprocessor
613 co-processor on the die.
616 will be called mxs-dcp.
668 (default), hashes-only, or skciphers-only.
671 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
672 QCE handles only 2 requests in parallel.
675 algorithms, sharing the load with the CPU. Enabling skciphers-only
685 - AES (CBC, CTR, ECB, XTS)
686 - 3DES (CBC, ECB)
687 - DES (CBC, ECB)
688 - SHA1, HMAC-SHA1
689 - SHA256, HMAC-SHA256
692 bool "Symmetric-key ciphers only"
695 Enable symmetric-key ciphers only:
696 - AES (CBC, CTR, ECB, XTS)
697 - 3DES (ECB, CBC)
698 - DES (ECB, CBC)
701 bool "Hash/HMAC only"
704 Enable hashes/HMAC algorithms only:
705 - SHA1, HMAC-SHA1
706 - SHA256, HMAC-SHA256
709 bool "AEAD algorithms only"
712 Enable AEAD algorithms only:
713 - authenc()
714 - ccm(aes)
715 - rfc4309(ccm(aes))
728 Considering the 256-bit ciphers, software is 2-3 times faster than
729 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
730 With 128-bit keys, the break-even point would be around 1024-bytes.
733 cost in CPU usage. The minimum recommended setting is 16-bytes
734 (1 AES block), since AES-GCM will fail if you set it lower.
737 Note that 192-bit keys are not supported by the hardware and are
750 module will be called qcom-rng. If unsure, say N.
794 Xilinx ZynqMP has AES-GCM engine used for symmetric key
816 Secure Processing Unit (SPU). The SPU driver registers skcipher,
822 tristate "Inside Secure's SafeXcel cryptographic engine driver"
837 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
838 engines designed by Inside Secure. It currently accelerates DES, 3DES and
841 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
844 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
857 Enables the driver for the on-chip crypto accelerator