Lines Matching +full:hardware +full:- +full:accelerated
1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Hardware crypto devices"
7 Say Y here to get to see options for hardware crypto devices and
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
104 down the use of the available crypto hardware.
130 This is the s390 hardware accelerated implementation of the
141 This is the s390 hardware accelerated implementation of the
142 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
151 This is the s390 hardware accelerated implementation of the
152 SHA256 secure hash standard (DFIPS 180-2).
161 This is the s390 hardware accelerated implementation of the
171 This is the s390 hardware accelerated implementation of the
181 This is the s390 hardware accelerated implementation of the
193 This is the s390 hardware accelerated implementation of the
194 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
196 As of z990 the ECB and CBC mode are hardware accelerated.
197 As of z196 the CTR mode is hardware accelerated.
205 This is the s390 hardware accelerated implementation of the
206 AES cipher algorithms (FIPS-197).
208 As of z9 the ECB and CBC modes are hardware accelerated
210 As of z10 the ECB and CBC modes are hardware accelerated
212 As of z196 the CTR mode is hardware accelerated for all AES
213 key sizes and XTS mode is hardware accelerated for 256 and
223 and uses triple-DES to generate secure random numbers like the
224 ANSI X9.17 standard. User-space programs access the
225 pseudo-random-number device through the char device /dev/prandom.
234 This is the s390 hardware accelerated implementation of GHASH,
240 tristate "CRC-32 algorithms"
245 Select this option if you want to use hardware accelerated
247 can optimize the computation of CRC-32 (IEEE 802.3 Ethernet)
248 and CRC-32C (Castagnoli).
264 sub-units. One set provides the Modular Arithmetic Unit,
347 tristate "Driver for IXP4xx crypto hardware acceleration"
380 This option provides the kernel-side support for the TRNG hardware
449 This driver provides kernel-side support through the
450 cryptographic API for the pseudo random number generator hardware
454 module will be called exynos-rng.
479 needed for small and zero-size messages.
487 This enables support for the NX hardware cryptographic accelerator
497 tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
500 Driver for ST-Ericsson UX500 crypto engine.
530 will be called atmel-aes.
543 will be called atmel-tdes.
556 will be called atmel-sha.
574 will be called atmel-ecc.
589 will be called atmel-sha204a.
613 co-processor on the die.
616 will be called mxs-dcp.
636 hardware. To compile this driver as a module, choose M here. The
668 (default), hashes-only, or skciphers-only.
671 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
675 algorithms, sharing the load with the CPU. Enabling skciphers-only
685 - AES (CBC, CTR, ECB, XTS)
686 - 3DES (CBC, ECB)
687 - DES (CBC, ECB)
688 - SHA1, HMAC-SHA1
689 - SHA256, HMAC-SHA256
692 bool "Symmetric-key ciphers only"
695 Enable symmetric-key ciphers only:
696 - AES (CBC, CTR, ECB, XTS)
697 - 3DES (ECB, CBC)
698 - DES (ECB, CBC)
705 - SHA1, HMAC-SHA1
706 - SHA256, HMAC-SHA256
713 - authenc()
714 - ccm(aes)
715 - rfc4309(ccm(aes))
727 Small blocks are processed faster in software than hardware.
728 Considering the 256-bit ciphers, software is 2-3 times faster than
729 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
730 With 128-bit keys, the break-even point would be around 1024-bytes.
733 cost in CPU usage. The minimum recommended setting is 16-bytes
734 (1 AES block), since AES-GCM will fail if you set it lower.
735 Setting this to zero will send all requests to the hardware.
737 Note that 192-bit keys are not supported by the hardware and are
739 are done by the hardware.
747 Generator hardware found on Qualcomm SoCs.
750 module will be called qcom-rng. If unsure, say N.
761 tristate "Imagination Technologies hardware hash accelerator"
769 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
784 This driver interfaces with the hardware crypto accelerator.
794 Xilinx ZynqMP has AES-GCM engine used for symmetric key
837 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
841 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
844 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
857 Enables the driver for the on-chip crypto accelerator
887 Choose this if you wish to use hardware acceleration of
910 used for crypto offload. Select this if you want to use hardware