Lines Matching +full:1000 +full:base +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0+
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
26 #include "cpufreq-dt.h"
66 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x)) argument
75 #define MIN_VOLT_MV 1000
111 /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
112 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
113 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
114 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
134 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base, in armada37xx_cpufreq_dvfs_setup() argument
168 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
183 regmap_update_bits(base, reg, mask, val); in armada37xx_cpufreq_dvfs_setup()
188 * Find out the armada 37x supported AVS value whose voltage value is
189 * the round-up closest to the target voltage value.
195 /* Find out the round-up closest supported voltage value */ in armada_37xx_avs_val_match()
205 avs = ARRAY_SIZE(avs_map) - 1; in armada_37xx_avs_val_match()
213 * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
215 * - L1 voltage should be about 100mv smaller than L0 voltage
216 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
219 * When base CPU frequency is 1000 or 1200 MHz then there is additional
222 static void __init armada37xx_cpufreq_avs_configure(struct regmap *base, in armada37xx_cpufreq_avs_configure() argument
229 if (base == NULL) in armada37xx_cpufreq_avs_configure()
233 regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min); in armada37xx_cpufreq_avs_configure()
240 dvfs->avs[0] = l0_vdd_min; in armada37xx_cpufreq_avs_configure()
244 * If L0 voltage is smaller than 1000mv, then all VDD sets in armada37xx_cpufreq_avs_configure()
250 dvfs->avs[load_level] = avs_min; in armada37xx_cpufreq_avs_configure()
253 * Set the avs values for load L0 and L1 when base CPU frequency in armada37xx_cpufreq_avs_configure()
254 * is 1000/1200 MHz to its typical initial values according to in armada37xx_cpufreq_avs_configure()
257 if (dvfs->cpu_freq_max >= 1000*1000*1000) { in armada37xx_cpufreq_avs_configure()
258 if (dvfs->cpu_freq_max >= 1200*1000*1000) in armada37xx_cpufreq_avs_configure()
262 dvfs->avs[0] = dvfs->avs[1] = avs_min; in armada37xx_cpufreq_avs_configure()
269 * L1 voltage is equal to L0 voltage - 100mv and it must be in armada37xx_cpufreq_avs_configure()
270 * larger than 1000mv in armada37xx_cpufreq_avs_configure()
273 target_vm = avs_map[l0_vdd_min] - 100; in armada37xx_cpufreq_avs_configure()
275 dvfs->avs[1] = armada_37xx_avs_val_match(target_vm); in armada37xx_cpufreq_avs_configure()
278 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must in armada37xx_cpufreq_avs_configure()
279 * be larger than 1000mv in armada37xx_cpufreq_avs_configure()
281 target_vm = avs_map[l0_vdd_min] - 150; in armada37xx_cpufreq_avs_configure()
283 dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm); in armada37xx_cpufreq_avs_configure()
286 * Fix the avs value for load L1 when base CPU frequency is 1000/1200 MHz, in armada37xx_cpufreq_avs_configure()
290 if (dvfs->cpu_freq_max >= 1000*1000*1000) { in armada37xx_cpufreq_avs_configure()
293 if (dvfs->cpu_freq_max >= 1200*1000*1000) in armada37xx_cpufreq_avs_configure()
298 if (avs_min_l1 > dvfs->avs[0]) in armada37xx_cpufreq_avs_configure()
299 avs_min_l1 = dvfs->avs[0]; in armada37xx_cpufreq_avs_configure()
301 if (dvfs->avs[1] < avs_min_l1) in armada37xx_cpufreq_avs_configure()
302 dvfs->avs[1] = avs_min_l1; in armada37xx_cpufreq_avs_configure()
306 static void __init armada37xx_cpufreq_avs_setup(struct regmap *base, in armada37xx_cpufreq_avs_setup() argument
312 if (base == NULL) in armada37xx_cpufreq_avs_setup()
316 regmap_update_bits(base, ARMADA_37XX_AVS_CTL0, in armada37xx_cpufreq_avs_setup()
321 regmap_update_bits(base, ARMADA_37XX_AVS_CTL2, in armada37xx_cpufreq_avs_setup()
327 avs_val = dvfs->avs[load_level]; in armada37xx_cpufreq_avs_setup()
328 regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1), in armada37xx_cpufreq_avs_setup()
336 regmap_update_bits(base, ARMADA_37XX_AVS_CTL0, in armada37xx_cpufreq_avs_setup()
342 static void armada37xx_cpufreq_disable_dvfs(struct regmap *base) in armada37xx_cpufreq_disable_dvfs() argument
347 regmap_update_bits(base, reg, mask, 0); in armada37xx_cpufreq_disable_dvfs()
350 static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base) in armada37xx_cpufreq_enable_dvfs() argument
357 regmap_update_bits(base, reg, mask, val); in armada37xx_cpufreq_enable_dvfs()
365 regmap_update_bits(base, reg, mask, mask); in armada37xx_cpufreq_enable_dvfs()
372 regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1); in armada37xx_cpufreq_suspend()
373 regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3); in armada37xx_cpufreq_suspend()
374 regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD, in armada37xx_cpufreq_suspend()
375 &state->nb_cpu_load); in armada37xx_cpufreq_suspend()
376 regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod); in armada37xx_cpufreq_suspend()
386 armada37xx_cpufreq_disable_dvfs(state->regmap); in armada37xx_cpufreq_resume()
388 regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1); in armada37xx_cpufreq_resume()
389 regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3); in armada37xx_cpufreq_resume()
390 regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD, in armada37xx_cpufreq_resume()
391 state->nb_cpu_load); in armada37xx_cpufreq_resume()
398 regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod); in armada37xx_cpufreq_resume()
416 syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb"); in armada37xx_cpufreq_driver_init()
418 return -ENODEV; in armada37xx_cpufreq_driver_init()
421 syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm"); in armada37xx_cpufreq_driver_init()
424 return -ENODEV; in armada37xx_cpufreq_driver_init()
427 syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs"); in armada37xx_cpufreq_driver_init()
445 return -ENODEV; in armada37xx_cpufreq_driver_init()
467 return -EINVAL; in armada37xx_cpufreq_driver_init()
473 return -EINVAL; in armada37xx_cpufreq_driver_init()
480 return -ENOMEM; in armada37xx_cpufreq_driver_init()
483 armada37xx_cpufreq_state->regmap = nb_pm_base; in armada37xx_cpufreq_driver_init()
488 armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider); in armada37xx_cpufreq_driver_init()
493 unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000; in armada37xx_cpufreq_driver_init()
494 freq = base_frequency / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_init()
509 pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata, in armada37xx_cpufreq_driver_init()
515 armada37xx_cpufreq_state->cpu_dev = cpu_dev; in armada37xx_cpufreq_driver_init()
516 armada37xx_cpufreq_state->pdev = pdev; in armada37xx_cpufreq_driver_init()
523 /* clean-up the already added opp before leaving */ in armada37xx_cpufreq_driver_init()
524 while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) { in armada37xx_cpufreq_driver_init()
525 freq = base_frequency / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_init()
538 struct platform_device *pdev = armada37xx_cpufreq_state->pdev; in armada37xx_cpufreq_driver_exit()
545 armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap); in armada37xx_cpufreq_driver_exit()
548 freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl]; in armada37xx_cpufreq_driver_exit()
549 dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq); in armada37xx_cpufreq_driver_exit()
557 { .compatible = "marvell,armada-3700-nb-pm" },
562 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");