1 // SPDX-License-Identifier: GPL-2.0
3  * STM32 Timer Encoder and Counter driver
11 #include <linux/mfd/stm32-timers.h>
40  * enum stm32_count_function - enumerates stm32 timer counter encoder modes
63 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_read()
66 	regmap_read(priv->regmap, TIM_CNT, &cnt);  in stm32_count_read()
76 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_write()
79 	regmap_read(priv->regmap, TIM_ARR, &ceiling);  in stm32_count_write()
81 		return -EINVAL;  in stm32_count_write()
83 	return regmap_write(priv->regmap, TIM_CNT, val);  in stm32_count_write()
90 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_function_get()
93 	regmap_read(priv->regmap, TIM_SMCR, &smcr);  in stm32_count_function_get()
109 		return -EINVAL;  in stm32_count_function_get()
117 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_function_set()
134 		return -EINVAL;  in stm32_count_function_set()
138 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_function_set()
140 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_function_set()
142 	regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);  in stm32_count_function_set()
145 	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);  in stm32_count_function_set()
148 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);  in stm32_count_function_set()
157 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_direction_read()
161 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_direction_read()
171 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_ceiling_read()
174 	regmap_read(priv->regmap, TIM_ARR, &arr);  in stm32_count_ceiling_read()
184 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_ceiling_write()
192 	if (ceiling > priv->max_arr)  in stm32_count_ceiling_write()
193 		return -ERANGE;  in stm32_count_ceiling_write()
196 	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);  in stm32_count_ceiling_write()
197 	regmap_write(priv->regmap, TIM_ARR, ceiling);  in stm32_count_ceiling_write()
206 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_enable_read()
209 	regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_read()
219 	struct stm32_timer_cnt *const priv = counter->priv;  in stm32_count_enable_write()
229 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
231 			clk_enable(priv->clk);  in stm32_count_enable_write()
233 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,  in stm32_count_enable_write()
236 		regmap_read(priv->regmap, TIM_CR1, &cr1);  in stm32_count_enable_write()
237 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_count_enable_write()
239 			clk_disable(priv->clk);  in stm32_count_enable_write()
243 	priv->enabled = enable;  in stm32_count_enable_write()
294 		if (synapse->signal->id == count->synapses[0].signal->id)  in stm32_action_get()
301 		if (synapse->signal->id == count->synapses[1].signal->id)  in stm32_action_get()
311 		return -EINVAL;  in stm32_action_get()
360 	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);  in stm32_timer_cnt_probe()
361 	struct device *dev = &pdev->dev;  in stm32_timer_cnt_probe()
365 		return -EINVAL;  in stm32_timer_cnt_probe()
369 		return -ENOMEM;  in stm32_timer_cnt_probe()
371 	priv->regmap = ddata->regmap;  in stm32_timer_cnt_probe()
372 	priv->clk = ddata->clk;  in stm32_timer_cnt_probe()
373 	priv->max_arr = ddata->max_arr;  in stm32_timer_cnt_probe()
375 	priv->counter.name = dev_name(dev);  in stm32_timer_cnt_probe()
376 	priv->counter.parent = dev;  in stm32_timer_cnt_probe()
377 	priv->counter.ops = &stm32_timer_cnt_ops;  in stm32_timer_cnt_probe()
378 	priv->counter.counts = &stm32_counts;  in stm32_timer_cnt_probe()
379 	priv->counter.num_counts = 1;  in stm32_timer_cnt_probe()
380 	priv->counter.signals = stm32_signals;  in stm32_timer_cnt_probe()
381 	priv->counter.num_signals = ARRAY_SIZE(stm32_signals);  in stm32_timer_cnt_probe()
382 	priv->counter.priv = priv;  in stm32_timer_cnt_probe()
387 	return devm_counter_register(dev, &priv->counter);  in stm32_timer_cnt_probe()
395 	if (priv->enabled) {  in stm32_timer_cnt_suspend()
397 		regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);  in stm32_timer_cnt_suspend()
398 		regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);  in stm32_timer_cnt_suspend()
399 		regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);  in stm32_timer_cnt_suspend()
400 		regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);  in stm32_timer_cnt_suspend()
403 		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);  in stm32_timer_cnt_suspend()
404 		clk_disable(priv->clk);  in stm32_timer_cnt_suspend()
419 	if (priv->enabled) {  in stm32_timer_cnt_resume()
420 		clk_enable(priv->clk);  in stm32_timer_cnt_resume()
423 		regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);  in stm32_timer_cnt_resume()
424 		regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);  in stm32_timer_cnt_resume()
425 		regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);  in stm32_timer_cnt_resume()
427 		/* Also re-enables the counter */  in stm32_timer_cnt_resume()
428 		regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);  in stm32_timer_cnt_resume()
438 	{ .compatible = "st,stm32-timer-counter", },
446 		.name = "stm32-timer-counter",
454 MODULE_ALIAS("platform:stm32-timer-counter");
455 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");