Lines Matching +full:interrupt +full:- +full:counter
1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
38 * 4 CTR-Z2 INTERRUPT
39 * 5 INTERRUPT
42 * ------------- -------------
44 * 0 CTR-X1 PPI-X
45 * 1 CTR-X2 PPI-Y
46 * 2 CTR-Y1 PPI-Z
47 * 3 CTR-Y2 INTERRUPT
48 * 4 CTR-Z1
49 * 5 CTR-Z2
50 * 6 INTERRUPT
55 * Port A - channels 0 to 7
56 * Port B - channels 8 to 15
57 * Port CL - channels 16 to 19
58 * Port CH - channels 20 to 23
62 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
69 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
73 * counter channel into data[1].
75 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
76 * specified in data[1] (this is a hardware-specific value). Not
80 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
81 * connector. (N.B. for other values, the counter channel's CLKn
88 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
89 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
90 * the SK1 connector. This pin is shared by all three counter
93 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
97 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
98 * specified in data[2] (this is a hardware-specific value). Not
104 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
105 * connector. (N.B. for other values, the counter channel's GATn
107 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
114 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
119 * 1. Clock source OUT n-1 is the output of the preceding channel on the
120 * same counter subdevice if n > 0, or the output of channel 2 on the
121 * preceding counter subdevice (see note 3) if n = 0.
123 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
124 * same counter subdevice if n = 2, or the inverted output of channel n+1
125 * on the preceding counter subdevice (see note 3) if n < 2.
127 * 3. The counter subdevices are connected in a ring, so the highest
128 * counter subdevice precedes the lowest.
130 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
131 * digital inputs come from the interrupt status register. The number of
132 * channels matches the number of interrupt sources. The PC214E does not
133 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
136 * INTERRUPT SOURCES
139 * ------------- ------------- -------------
141 * 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
142 * 1 PPI-X-C3 PPI-X-C3
143 * 2 CTR-Y1-OUT1 PPI-Y-C0
144 * 3 CTR-Y2-OUT1 PPI-Y-C3
145 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
146 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
149 * ------------- -------------
151 * 0 CTR-X1-OUT1 PPI-X-C0
152 * 1 CTR-X2-OUT1 PPI-X-C3
153 * 2 CTR-Y1-OUT1 PPI-Y-C0
154 * 3 CTR-Y2-OUT1 PPI-Y-C3
155 * 4 CTR-Z1-OUT1 PPI-Z-C0
156 * 5 CTR-Z2-OUT1 PPI-Z-C3
158 * When an interrupt source is enabled in the interrupt source enable
160 * bit to 1 in the interrupt status register.
162 * When the interrupt status register value as a whole (actually, just the
163 * 6 least significant bits) goes from zero to non-zero, the board will
164 * generate an interrupt. No further interrupts will occur until the
165 * interrupt status register is cleared to zero. To clear a bit to zero in
166 * the interrupt status register, the corresponding interrupt source must
167 * be disabled in the interrupt source enable register (there is no
168 * separate interrupt clear register).
170 * The PC214E does not have an interrupt source enable register or an
171 * interrupt status register; its 'INTERRUPT' subdevice has a single
172 * channel and its interrupt source is selected by the position of jumper
178 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
180 * TRIG_NOW). The scan begins a short time after the hardware interrupt
181 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
182 * scan_begin_arg == 0). The value read from the interrupt status register
245 ret = comedi_request_region(dev, it->options[0], 0x20); in dio200_attach()
249 return amplc_dio200_common_attach(dev, it->options[1], 0); in dio200_attach()