Lines Matching +full:clock +full:- +full:name
1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
18 #include "clk-zynqmp.h"
48 * struct clock_parent - Clock parent
49 * @name: Parent name
50 * @id: Parent clock ID
54 char name[MAX_NAME_LEN]; member
60 * struct zynqmp_clock - Clock
61 * @clk_name: Clock name
62 * @valid: Validity flag of clock
63 * @type: Clock type (Output/External)
64 * @node: Clock topology nodes
66 * @parent: Parent of clock
67 * @num_parents: Number of parents of clock
68 * @clk_id: Clock id
82 char name[CLK_GET_NAME_RESP_LEN]; member
121 static struct clk_hw *(* const clk_topology[]) (const char *name, u32 clk_id,
135 static struct zynqmp_clock *clock; variable
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
141 * @clk_id: Clock index
143 * Return: 1 if clock is valid, 0 if clock is invalid else error code
148 return -ENODEV; in zynqmp_is_valid_clock()
150 return clock[clk_id].valid; in zynqmp_is_valid_clock()
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
155 * @clk_id: Clock index
156 * @clk_name: Name of clock
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
170 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_name()
174 * zynqmp_get_clock_type() - Get type of clock
175 * @clk_id: Clock index
176 * @type: Clock type: CLK_TYPE_OUTPUT or CLK_TYPE_EXTERNAL
186 *type = clock[clk_id].type; in zynqmp_get_clock_type()
190 return ret == 0 ? -EINVAL : ret; in zynqmp_get_clock_type()
194 * zynqmp_pm_clock_get_num_clocks() - Get number of clocks in system
216 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
217 * @clock_id: ID of the clock to be queried
218 * @response: Name of the clock with the given id
220 * This function is used to get name of clock specified by given
221 * clock ID.
241 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
242 * @clock_id: ID of the clock to be queried
243 * @index: Node index of clock topology
246 * This function is used to get topology information for the clock
247 * specified by given clock ID.
295 * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
296 * clock framework
297 * @name: Name of this clock
298 * @clk_id: Clock ID
299 * @parents: Name of this clock's parents
301 * @nodes: Clock topology node
303 * Return: clock hardware to the registered clock
305 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, in zynqmp_clk_register_fixed_factor() argument
327 flag = zynqmp_clk_map_common_ccf_flags(nodes->flag); in zynqmp_clk_register_fixed_factor()
329 hw = clk_hw_register_fixed_factor(NULL, name, in zynqmp_clk_register_fixed_factor()
338 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
339 * @clock_id: Clock ID
341 * @response: Parents of the given clock
343 * This function is used to get 3 parents for the clock specified by
344 * given clock ID.
372 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
373 * @clock_id: Clock ID
374 * @response: Clock attributes response
376 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
397 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
399 * @topology: Clock topology
400 * @response: Clock topology data received from firmware
412 for (i = 0; i < ARRAY_SIZE(response->topology); i++) { in __zynqmp_clock_get_topology()
413 type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]); in __zynqmp_clock_get_topology()
418 response->topology[i]); in __zynqmp_clock_get_topology()
421 response->topology[i]); in __zynqmp_clock_get_topology()
424 response->topology[i]); in __zynqmp_clock_get_topology()
432 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
434 * @clk_id: Clock index
435 * @topology: Clock topology
449 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j, in zynqmp_clock_get_topology()
463 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
465 * @parents: Clock parents
466 * @response: Clock parents data received from firmware
478 for (i = 0; i < ARRAY_SIZE(response->parents); i++) { in __zynqmp_clock_get_parents()
479 if (response->parents[i] == NA_PARENT) in __zynqmp_clock_get_parents()
483 parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]); in __zynqmp_clock_get_parents()
484 if (response->parents[i] == DUMMY_PARENT) { in __zynqmp_clock_get_parents()
485 strcpy(parent->name, "dummy_name"); in __zynqmp_clock_get_parents()
486 parent->flag = 0; in __zynqmp_clock_get_parents()
488 parent->flag = FIELD_GET(CLK_PARENTS_FLAGS, in __zynqmp_clock_get_parents()
489 response->parents[i]); in __zynqmp_clock_get_parents()
490 if (zynqmp_get_clock_name(parent->id, parent->name)) in __zynqmp_clock_get_parents()
500 * zynqmp_clock_get_parents() - Get parents info from firmware using PM_API
501 * @clk_id: Clock index
502 * @parents: Clock parents
516 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j, in zynqmp_clock_get_parents()
532 * zynqmp_get_parent_list() - Create list of parents name
534 * @clk_id: Clock index
535 * @parent_list: List of parent's name
544 u32 total_parents = clock[clk_id].num_parents; in zynqmp_get_parent_list()
548 clk_nodes = clock[clk_id].node; in zynqmp_get_parent_list()
549 parents = clock[clk_id].parent; in zynqmp_get_parent_list()
553 parent_list[i] = parents[i].name; in zynqmp_get_parent_list()
555 ret = of_property_match_string(np, "clock-names", in zynqmp_get_parent_list()
556 parents[i].name); in zynqmp_get_parent_list()
558 strcpy(parents[i].name, "dummy_name"); in zynqmp_get_parent_list()
559 parent_list[i] = parents[i].name; in zynqmp_get_parent_list()
561 strcat(parents[i].name, in zynqmp_get_parent_list()
562 clk_type_postfix[clk_nodes[parents[i].flag - 1]. in zynqmp_get_parent_list()
564 parent_list[i] = parents[i].name; in zynqmp_get_parent_list()
573 * zynqmp_register_clk_topology() - Register clock topology
574 * @clk_id: Clock index
575 * @clk_name: Clock Name
577 * @parent_names: List of parents name
579 * Return: Returns either clock hardware or error+reason
591 nodes = clock[clk_id].node; in zynqmp_register_clk_topology()
592 num_nodes = clock[clk_id].num_nodes; in zynqmp_register_clk_topology()
593 clk_dev_id = clock[clk_id].clk_id; in zynqmp_register_clk_topology()
597 * Clock name received from firmware is output clock name. in zynqmp_register_clk_topology()
598 * Intermediate clock names are postfixed with type of clock. in zynqmp_register_clk_topology()
600 if (j != (num_nodes - 1)) { in zynqmp_register_clk_topology()
629 * zynqmp_register_clocks() - Register clocks
643 /* get clock name, continue to next clock if name not found */ in zynqmp_register_clocks()
647 /* Check if clock is valid and output clock. in zynqmp_register_clocks()
648 * Do not register invalid or external clock. in zynqmp_register_clocks()
654 /* Get parents of clock*/ in zynqmp_register_clocks()
658 clock[i].clk_name); in zynqmp_register_clocks()
662 zynqmp_data->hws[i] = in zynqmp_register_clocks()
669 if (IS_ERR(zynqmp_data->hws[i])) { in zynqmp_register_clocks()
671 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i])); in zynqmp_register_clocks()
679 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
687 struct name_resp name; in zynqmp_get_clock_info() local
694 clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]); in zynqmp_get_clock_info()
695 /* skip query for Invalid clock */ in zynqmp_get_clock_info()
700 clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ? in zynqmp_get_clock_info()
707 clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) | in zynqmp_get_clock_info()
712 zynqmp_pm_clock_get_name(clock[i].clk_id, &name); in zynqmp_get_clock_info()
713 if (!strcmp(name.name, RESERVED_CLK_NAME)) in zynqmp_get_clock_info()
715 strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN); in zynqmp_get_clock_info()
718 /* Get topology of all clock */ in zynqmp_get_clock_info()
724 ret = zynqmp_clock_get_topology(i, clock[i].node, in zynqmp_get_clock_info()
725 &clock[i].num_nodes); in zynqmp_get_clock_info()
729 ret = zynqmp_clock_get_parents(i, clock[i].parent, in zynqmp_get_clock_info()
730 &clock[i].num_parents); in zynqmp_get_clock_info()
737 * zynqmp_clk_setup() - Setup the clock framework and register clocks
753 return -ENOMEM; in zynqmp_clk_setup()
755 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL); in zynqmp_clk_setup()
756 if (!clock) { in zynqmp_clk_setup()
758 return -ENOMEM; in zynqmp_clk_setup()
764 zynqmp_data->num = clock_max_idx; in zynqmp_clk_setup()
771 struct device *dev = &pdev->dev; in zynqmp_clock_probe()
773 ret = zynqmp_clk_setup(dev->of_node); in zynqmp_clock_probe()
779 {.compatible = "xlnx,zynqmp-clk"},
780 {.compatible = "xlnx,versal-clk"},
787 .name = "zynqmp_clock",