170 	clk = of_clk_get(node, 0);  in _register_dpll()
233 	parent_name = of_clk_get_parent_name(node, 0);  in _register_dpll_x2()
258 		if (ret <= 0) {  in _register_dpll_x2()
260 		} else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {  in _register_dpll_x2()
294 	u8 dpll_mode = 0;  in of_ti_dpll_setup()
324 	if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))  in of_ti_dpll_setup()
422 		.idlest_mask = 0x1,  in of_ti_omap3_dpll_setup()
423 		.enable_mask = 0x7,  in of_ti_omap3_dpll_setup()
424 		.autoidle_mask = 0x7,  in of_ti_omap3_dpll_setup()
425 		.mult_mask = 0x7ff << 8,  in of_ti_omap3_dpll_setup()
426 		.div1_mask = 0x7f,  in of_ti_omap3_dpll_setup()
430 		.freqsel_mask = 0xf0,  in of_ti_omap3_dpll_setup()
447 		.idlest_mask = 0x1,  in of_ti_omap3_core_dpll_setup()
448 		.enable_mask = 0x7,  in of_ti_omap3_core_dpll_setup()
449 		.autoidle_mask = 0x7,  in of_ti_omap3_core_dpll_setup()
450 		.mult_mask = 0x7ff << 16,  in of_ti_omap3_core_dpll_setup()
451 		.div1_mask = 0x7f << 8,  in of_ti_omap3_core_dpll_setup()
455 		.freqsel_mask = 0xf0,  in of_ti_omap3_core_dpll_setup()
466 		.idlest_mask = 0x1 << 1,  in of_ti_omap3_per_dpll_setup()
467 		.enable_mask = 0x7 << 16,  in of_ti_omap3_per_dpll_setup()
468 		.autoidle_mask = 0x7 << 3,  in of_ti_omap3_per_dpll_setup()
469 		.mult_mask = 0x7ff << 8,  in of_ti_omap3_per_dpll_setup()
470 		.div1_mask = 0x7f,  in of_ti_omap3_per_dpll_setup()
474 		.freqsel_mask = 0xf00000,  in of_ti_omap3_per_dpll_setup()
486 		.idlest_mask = 0x1 << 1,  in of_ti_omap3_per_jtype_dpll_setup()
487 		.enable_mask = 0x7 << 16,  in of_ti_omap3_per_jtype_dpll_setup()
488 		.autoidle_mask = 0x7 << 3,  in of_ti_omap3_per_jtype_dpll_setup()
489 		.mult_mask = 0xfff << 8,  in of_ti_omap3_per_jtype_dpll_setup()
490 		.div1_mask = 0x7f,  in of_ti_omap3_per_jtype_dpll_setup()
494 		.sddiv_mask = 0xff << 24,  in of_ti_omap3_per_jtype_dpll_setup()
495 		.dco_mask = 0xe << 20,  in of_ti_omap3_per_jtype_dpll_setup()
509 		.idlest_mask = 0x1,  in of_ti_omap4_dpll_setup()
510 		.enable_mask = 0x7,  in of_ti_omap4_dpll_setup()
511 		.autoidle_mask = 0x7,  in of_ti_omap4_dpll_setup()
512 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_dpll_setup()
513 		.div1_mask = 0x7f,  in of_ti_omap4_dpll_setup()
528 		.idlest_mask = 0x1,  in of_ti_omap5_mpu_dpll_setup()
529 		.enable_mask = 0x7,  in of_ti_omap5_mpu_dpll_setup()
530 		.autoidle_mask = 0x7,  in of_ti_omap5_mpu_dpll_setup()
531 		.mult_mask = 0x7ff << 8,  in of_ti_omap5_mpu_dpll_setup()
532 		.div1_mask = 0x7f,  in of_ti_omap5_mpu_dpll_setup()
549 		.idlest_mask = 0x1,  in of_ti_omap4_core_dpll_setup()
550 		.enable_mask = 0x7,  in of_ti_omap4_core_dpll_setup()
551 		.autoidle_mask = 0x7,  in of_ti_omap4_core_dpll_setup()
552 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_core_dpll_setup()
553 		.div1_mask = 0x7f,  in of_ti_omap4_core_dpll_setup()
570 		.idlest_mask = 0x1,  in of_ti_omap4_m4xen_dpll_setup()
571 		.enable_mask = 0x7,  in of_ti_omap4_m4xen_dpll_setup()
572 		.autoidle_mask = 0x7,  in of_ti_omap4_m4xen_dpll_setup()
573 		.mult_mask = 0x7ff << 8,  in of_ti_omap4_m4xen_dpll_setup()
574 		.div1_mask = 0x7f,  in of_ti_omap4_m4xen_dpll_setup()
578 		.m4xen_mask = 0x800,  in of_ti_omap4_m4xen_dpll_setup()
591 		.idlest_mask = 0x1,  in of_ti_omap4_jtype_dpll_setup()
592 		.enable_mask = 0x7,  in of_ti_omap4_jtype_dpll_setup()
593 		.autoidle_mask = 0x7,  in of_ti_omap4_jtype_dpll_setup()
594 		.mult_mask = 0xfff << 8,  in of_ti_omap4_jtype_dpll_setup()
595 		.div1_mask = 0xff,  in of_ti_omap4_jtype_dpll_setup()
599 		.sddiv_mask = 0xff << 24,  in of_ti_omap4_jtype_dpll_setup()
613 		.idlest_mask = 0x1,  in of_ti_am3_no_gate_dpll_setup()
614 		.enable_mask = 0x7,  in of_ti_am3_no_gate_dpll_setup()
615 		.ssc_enable_mask = 0x1 << 12,  in of_ti_am3_no_gate_dpll_setup()
616 		.ssc_downspread_mask = 0x1 << 14,  in of_ti_am3_no_gate_dpll_setup()
617 		.mult_mask = 0x7ff << 8,  in of_ti_am3_no_gate_dpll_setup()
618 		.div1_mask = 0x7f,  in of_ti_am3_no_gate_dpll_setup()
619 		.ssc_deltam_int_mask = 0x3 << 18,  in of_ti_am3_no_gate_dpll_setup()
620 		.ssc_deltam_frac_mask = 0x3ffff,  in of_ti_am3_no_gate_dpll_setup()
621 		.ssc_modfreq_mant_mask = 0x7f,  in of_ti_am3_no_gate_dpll_setup()
622 		.ssc_modfreq_exp_mask = 0x7 << 8,  in of_ti_am3_no_gate_dpll_setup()
638 		.idlest_mask = 0x1,  in of_ti_am3_jtype_dpll_setup()
639 		.enable_mask = 0x7,  in of_ti_am3_jtype_dpll_setup()
640 		.mult_mask = 0x7ff << 8,  in of_ti_am3_jtype_dpll_setup()
641 		.div1_mask = 0x7f,  in of_ti_am3_jtype_dpll_setup()
658 		.idlest_mask = 0x1,  in of_ti_am3_no_gate_jtype_dpll_setup()
659 		.enable_mask = 0x7,  in of_ti_am3_no_gate_jtype_dpll_setup()
660 		.mult_mask = 0x7ff << 8,  in of_ti_am3_no_gate_jtype_dpll_setup()
661 		.div1_mask = 0x7f,  in of_ti_am3_no_gate_jtype_dpll_setup()
679 		.idlest_mask = 0x1,  in of_ti_am3_dpll_setup()
680 		.enable_mask = 0x7,  in of_ti_am3_dpll_setup()
681 		.ssc_enable_mask = 0x1 << 12,  in of_ti_am3_dpll_setup()
682 		.ssc_downspread_mask = 0x1 << 14,  in of_ti_am3_dpll_setup()
683 		.mult_mask = 0x7ff << 8,  in of_ti_am3_dpll_setup()
684 		.div1_mask = 0x7f,  in of_ti_am3_dpll_setup()
685 		.ssc_deltam_int_mask = 0x3 << 18,  in of_ti_am3_dpll_setup()
686 		.ssc_deltam_frac_mask = 0x3ffff,  in of_ti_am3_dpll_setup()
687 		.ssc_modfreq_mant_mask = 0x7f,  in of_ti_am3_dpll_setup()
688 		.ssc_modfreq_exp_mask = 0x7 << 8,  in of_ti_am3_dpll_setup()
703 		.idlest_mask = 0x1,  in of_ti_am3_core_dpll_setup()
704 		.enable_mask = 0x7,  in of_ti_am3_core_dpll_setup()
705 		.mult_mask = 0x7ff << 8,  in of_ti_am3_core_dpll_setup()
706 		.div1_mask = 0x7f,  in of_ti_am3_core_dpll_setup()
722 		.enable_mask = 0x3,  in of_ti_omap2_core_dpll_setup()
723 		.mult_mask = 0x3ff << 12,  in of_ti_omap2_core_dpll_setup()
724 		.div1_mask = 0xf << 8,  in of_ti_omap2_core_dpll_setup()