Lines Matching full:24
55 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
82 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
87 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
92 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
109 { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
110 { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
111 { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
112 { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
114 { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
161 "atl_cm:clk:0000:24",
166 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
254 "l3init_cm:clk:0008:24",
265 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
271 "l3init_cm:clk:0010:24",
282 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
347 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
389 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
394 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
399 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
404 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
409 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
414 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
444 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
449 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
454 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
469 "l4per_cm:clk:0120:24",
480 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
486 "l4per_cm:clk:0128:24",
497 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
503 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
514 "l4per_cm:clk:0138:24",
524 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
530 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
535 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
540 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
545 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
551 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
558 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
563 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
569 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
581 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
602 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
608 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
615 { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
616 { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
617 { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
618 { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
619 { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
620 { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
636 …{ DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm"…
637 …{ DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm"…
638 …{ DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm"…
647 …{ DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm"…
649 { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
650 { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
651 { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
652 { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
655 { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
657 { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
664 { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
665 { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
666 { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
679 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
684 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
695 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
703 { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
706 { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
707 { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
734 DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
736 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
753 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
756 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
758 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
760 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
762 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
764 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
766 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
769 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
772 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
775 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
778 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
781 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
789 DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
790 DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
792 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
793 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
794 DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
795 DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
796 DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
797 DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
798 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
799 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
800 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
801 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
802 DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
803 DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
804 DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
805 DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
806 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
807 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
808 DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
809 DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
810 DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
811 DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
812 DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
813 DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
814 DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
815 DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
816 DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),