1 // SPDX-License-Identifier: GPL-2.0-only
3  * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48  * When we change the timing to a timing with a parent that has the same
50  * timing that has a different clock source.
105 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_recalc_rate()
120 	struct emc_timing *timing = NULL;  in emc_determine_rate()  local
125 	for (k = 0; k < tegra->num_timings; k++) {  in emc_determine_rate()
126 		if (tegra->timings[k].ram_code == ram_code)  in emc_determine_rate()
130 	for (t = k; t < tegra->num_timings; t++) {  in emc_determine_rate()
131 		if (tegra->timings[t].ram_code != ram_code)  in emc_determine_rate()
136 		timing = tegra->timings + i;  in emc_determine_rate()
138 		if (timing->rate < req->rate && i != t - 1)  in emc_determine_rate()
141 		if (timing->rate > req->max_rate) {  in emc_determine_rate()
143 			req->rate = tegra->timings[i - 1].rate;  in emc_determine_rate()
147 		if (timing->rate < req->min_rate)  in emc_determine_rate()
150 		req->rate = timing->rate;  in emc_determine_rate()
154 	if (timing) {  in emc_determine_rate()
155 		req->rate = timing->rate;  in emc_determine_rate()
159 	req->rate = clk_hw_get_rate(hw);  in emc_determine_rate()
170 	val = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_get_parent()
180 	if (tegra->emc)  in emc_ensure_emc_driver()
181 		return tegra->emc;  in emc_ensure_emc_driver()
183 	if (!tegra->prepare_timing_change || !tegra->complete_timing_change)  in emc_ensure_emc_driver()
186 	if (!tegra->emc_node)  in emc_ensure_emc_driver()
189 	pdev = of_find_device_by_node(tegra->emc_node);  in emc_ensure_emc_driver()
196 	of_node_put(tegra->emc_node);  in emc_ensure_emc_driver()
197 	tegra->emc_node = NULL;  in emc_ensure_emc_driver()
199 	tegra->emc = platform_get_drvdata(pdev);  in emc_ensure_emc_driver()
200 	if (!tegra->emc) {  in emc_ensure_emc_driver()
205 	return tegra->emc;  in emc_ensure_emc_driver()
209 			  struct emc_timing *timing)  in emc_set_timing()  argument
218 		return -ENOENT;  in emc_set_timing()
220 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,  in emc_set_timing()
221 		 timing->parent_rate, __clk_get_name(timing->parent));  in emc_set_timing()
223 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
224 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_timing()
226 			  __clk_get_name(timing->parent),  in emc_set_timing()
227 			  clk_get_rate(timing->parent),  in emc_set_timing()
228 			  timing->parent_rate);  in emc_set_timing()
229 		return -EINVAL;  in emc_set_timing()
232 	tegra->changing_timing = true;  in emc_set_timing()
234 	err = clk_set_rate(timing->parent, timing->parent_rate);  in emc_set_timing()
237 		       __clk_get_name(timing->parent), timing->parent_rate,  in emc_set_timing()
243 	err = clk_prepare_enable(timing->parent);  in emc_set_timing()
249 	div = timing->parent_rate / (timing->rate / 2) - 2;  in emc_set_timing()
251 	err = tegra->prepare_timing_change(emc, timing->rate);  in emc_set_timing()
253 		clk_disable_unprepare(timing->parent);  in emc_set_timing()
257 	spin_lock_irqsave(tegra->lock, flags);  in emc_set_timing()
259 	car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
262 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);  in emc_set_timing()
267 	writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);  in emc_set_timing()
269 	spin_unlock_irqrestore(tegra->lock, flags);  in emc_set_timing()
271 	tegra->complete_timing_change(emc, timing->rate);  in emc_set_timing()
273 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
274 	clk_disable_unprepare(tegra->prev_parent);  in emc_set_timing()
276 	tegra->prev_parent = timing->parent;  in emc_set_timing()
277 	tegra->changing_timing = false;  in emc_set_timing()
283  * Get backup timing to use as an intermediate step when a change between
285  * find a timing with a higher clock rate to avoid a rate below any set rate
293 	struct emc_timing *timing;  in get_backup_timing()  local
295 	for (i = timing_index+1; i < tegra->num_timings; i++) {  in get_backup_timing()
296 		timing = tegra->timings + i;  in get_backup_timing()
297 		if (timing->ram_code != ram_code)  in get_backup_timing()
300 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
302 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
303 			return timing;  in get_backup_timing()
306 	for (i = timing_index-1; i >= 0; --i) {  in get_backup_timing()
307 		timing = tegra->timings + i;  in get_backup_timing()
308 		if (timing->ram_code != ram_code)  in get_backup_timing()
311 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
313 		      tegra->timings[timing_index].parent_index])  in get_backup_timing()
314 			return timing;  in get_backup_timing()
324 	struct emc_timing *timing = NULL;  in emc_set_rate()  local
338 	if (tegra->changing_timing)  in emc_set_rate()
341 	for (i = 0; i < tegra->num_timings; i++) {  in emc_set_rate()
342 		if (tegra->timings[i].rate == rate &&  in emc_set_rate()
343 		    tegra->timings[i].ram_code == ram_code) {  in emc_set_rate()
344 			timing = tegra->timings + i;  in emc_set_rate()
349 	if (!timing) {  in emc_set_rate()
351 		return -EINVAL;  in emc_set_rate()
355 	    emc_parent_clk_sources[timing->parent_index] &&  in emc_set_rate()
356 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_rate()
366 			pr_err("cannot find backup timing\n");  in emc_set_rate()
367 			return -EINVAL;  in emc_set_rate()
371 			 backup_timing->rate, rate);  in emc_set_rate()
375 			pr_err("cannot set backup timing: %d\n", err);  in emc_set_rate()
380 	return emc_set_timing(tegra, timing);  in emc_set_rate()
386 				   struct emc_timing *timing,  in load_one_timing_from_dt()  argument
392 	err = of_property_read_u32(node, "clock-frequency", &tmp);  in load_one_timing_from_dt()
394 		pr_err("timing %pOF: failed to read rate\n", node);  in load_one_timing_from_dt()
398 	timing->rate = tmp;  in load_one_timing_from_dt()
400 	err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);  in load_one_timing_from_dt()
402 		pr_err("timing %pOF: failed to read parent rate\n", node);  in load_one_timing_from_dt()
406 	timing->parent_rate = tmp;  in load_one_timing_from_dt()
408 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
409 	if (IS_ERR(timing->parent)) {  in load_one_timing_from_dt()
410 		pr_err("timing %pOF: failed to get parent clock\n", node);  in load_one_timing_from_dt()
411 		return PTR_ERR(timing->parent);  in load_one_timing_from_dt()
414 	timing->parent_index = 0xff;  in load_one_timing_from_dt()
416 			 __clk_get_name(timing->parent));  in load_one_timing_from_dt()
418 		pr_err("timing %pOF: %s is not a valid parent\n",  in load_one_timing_from_dt()
419 		       node, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
420 		clk_put(timing->parent);  in load_one_timing_from_dt()
421 		return -EINVAL;  in load_one_timing_from_dt()
424 	timing->parent_index = i;  in load_one_timing_from_dt()
433 	if (a->rate < b->rate)  in cmp_timings()
434 		return -1;  in cmp_timings()
435 	else if (a->rate == b->rate)  in cmp_timings()
451 	size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);  in load_timings_from_dt()
453 	tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);  in load_timings_from_dt()
454 	if (!tegra->timings)  in load_timings_from_dt()
455 		return -ENOMEM;  in load_timings_from_dt()
457 	timings_ptr = tegra->timings + tegra->num_timings;  in load_timings_from_dt()
458 	tegra->num_timings += child_count;  in load_timings_from_dt()
461 		struct emc_timing *timing = timings_ptr + (i++);  in load_timings_from_dt()  local
463 		err = load_one_timing_from_dt(tegra, timing, child);  in load_timings_from_dt()
469 		timing->ram_code = ram_code;  in load_timings_from_dt()
497 		return ERR_PTR(-ENOMEM);  in tegra124_clk_register_emc()
499 	tegra->clk_regs = base;  in tegra124_clk_register_emc()
500 	tegra->lock = lock;  in tegra124_clk_register_emc()
502 	tegra->num_timings = 0;  in tegra124_clk_register_emc()
505 		err = of_property_read_u32(node, "nvidia,ram-code",  in tegra124_clk_register_emc()
521 	if (tegra->num_timings == 0)  in tegra124_clk_register_emc()
524 	tegra->emc_node = of_parse_phandle(np,  in tegra124_clk_register_emc()
525 			"nvidia,external-memory-controller", 0);  in tegra124_clk_register_emc()
526 	if (!tegra->emc_node)  in tegra124_clk_register_emc()
535 	tegra->hw.init = &init;  in tegra124_clk_register_emc()
537 	clk = clk_register(NULL, &tegra->hw);  in tegra124_clk_register_emc()
541 	tegra->prev_parent = clk_hw_get_parent_by_index(  in tegra124_clk_register_emc()
542 		&tegra->hw, emc_get_parent(&tegra->hw))->clk;  in tegra124_clk_register_emc()
543 	tegra->changing_timing = false;  in tegra124_clk_register_emc()
546 	clk_register_clkdev(clk, "emc", "tegra-clk-debug");  in tegra124_clk_register_emc()
562 		tegra->prepare_timing_change = prep_cb;  in tegra124_clk_set_emc_callbacks()
563 		tegra->complete_timing_change = complete_cb;  in tegra124_clk_set_emc_callbacks()
572 	return tegra->prepare_timing_change && tegra->complete_timing_change;  in tegra124_clk_emc_driver_available()