48  * When we change the timing to a timing with a parent that has the same
50  * timing that has a different clock source.
120 	struct emc_timing *timing = NULL;  in emc_determine_rate()  local
136 		timing = tegra->timings + i;  in emc_determine_rate()
138 		if (timing->rate < req->rate && i != t - 1)  in emc_determine_rate()
141 		if (timing->rate > req->max_rate) {  in emc_determine_rate()
147 		if (timing->rate < req->min_rate)  in emc_determine_rate()
150 		req->rate = timing->rate;  in emc_determine_rate()
154 	if (timing) {  in emc_determine_rate()
155 		req->rate = timing->rate;  in emc_determine_rate()
209 			  struct emc_timing *timing)  in emc_set_timing()  argument
220 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,  in emc_set_timing()
221 		 timing->parent_rate, __clk_get_name(timing->parent));  in emc_set_timing()
223 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
224 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_timing()
226 			  __clk_get_name(timing->parent),  in emc_set_timing()
227 			  clk_get_rate(timing->parent),  in emc_set_timing()
228 			  timing->parent_rate);  in emc_set_timing()
234 	err = clk_set_rate(timing->parent, timing->parent_rate);  in emc_set_timing()
237 		       __clk_get_name(timing->parent), timing->parent_rate,  in emc_set_timing()
243 	err = clk_prepare_enable(timing->parent);  in emc_set_timing()
249 	div = timing->parent_rate / (timing->rate / 2) - 2;  in emc_set_timing()
251 	err = tegra->prepare_timing_change(emc, timing->rate);  in emc_set_timing()
253 		clk_disable_unprepare(timing->parent);  in emc_set_timing()
262 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);  in emc_set_timing()
271 	tegra->complete_timing_change(emc, timing->rate);  in emc_set_timing()
273 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
276 	tegra->prev_parent = timing->parent;  in emc_set_timing()
283  * Get backup timing to use as an intermediate step when a change between
285  * find a timing with a higher clock rate to avoid a rate below any set rate
293 	struct emc_timing *timing;  in get_backup_timing()  local
296 		timing = tegra->timings + i;  in get_backup_timing()
297 		if (timing->ram_code != ram_code)  in get_backup_timing()
300 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
303 			return timing;  in get_backup_timing()
307 		timing = tegra->timings + i;  in get_backup_timing()
308 		if (timing->ram_code != ram_code)  in get_backup_timing()
311 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
314 			return timing;  in get_backup_timing()
324 	struct emc_timing *timing = NULL;  in emc_set_rate()  local
344 			timing = tegra->timings + i;  in emc_set_rate()
349 	if (!timing) {  in emc_set_rate()
355 	    emc_parent_clk_sources[timing->parent_index] &&  in emc_set_rate()
356 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_rate()
366 			pr_err("cannot find backup timing\n");  in emc_set_rate()
375 			pr_err("cannot set backup timing: %d\n", err);  in emc_set_rate()
380 	return emc_set_timing(tegra, timing);  in emc_set_rate()
386 				   struct emc_timing *timing,  in load_one_timing_from_dt()  argument
394 		pr_err("timing %pOF: failed to read rate\n", node);  in load_one_timing_from_dt()
398 	timing->rate = tmp;  in load_one_timing_from_dt()
402 		pr_err("timing %pOF: failed to read parent rate\n", node);  in load_one_timing_from_dt()
406 	timing->parent_rate = tmp;  in load_one_timing_from_dt()
408 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
409 	if (IS_ERR(timing->parent)) {  in load_one_timing_from_dt()
410 		pr_err("timing %pOF: failed to get parent clock\n", node);  in load_one_timing_from_dt()
411 		return PTR_ERR(timing->parent);  in load_one_timing_from_dt()
414 	timing->parent_index = 0xff;  in load_one_timing_from_dt()
416 			 __clk_get_name(timing->parent));  in load_one_timing_from_dt()
418 		pr_err("timing %pOF: %s is not a valid parent\n",  in load_one_timing_from_dt()
419 		       node, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
420 		clk_put(timing->parent);  in load_one_timing_from_dt()
424 	timing->parent_index = i;  in load_one_timing_from_dt()
461 		struct emc_timing *timing = timings_ptr + (i++);  in load_timings_from_dt()  local
463 		err = load_one_timing_from_dt(tegra, timing, child);  in load_timings_from_dt()
469 		timing->ram_code = ram_code;  in load_timings_from_dt()