Lines Matching +full:reference +full:- +full:select

1 // SPDX-License-Identifier: GPL-2.0-or-later
6  * Copyright 2013 Chen-Yu Tsai
7  * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19  * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23  *  MII TX clock from PHY >-----|___________    _________|----> to GMAC core
24  *  GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25  *  Ext. 125MHz RGMII TX clk >--|__divider__/            |
28  * The external 125 MHz reference is optional, i.e. GMAC can use its
30  * the divider controls for the external reference.
34  * select the appropriate source and gate/ungate the output to the PHY.
40  * driver then responds by auto-reparenting the clock.
48 	0x00, /* Select mii_phy_tx_clk */
49 	0x02, /* Select gmac_int_tx_clk */
57 	const char *clk_name = node->name;  in sun7i_a20_gmac_clk_setup()
61 	if (of_property_read_string(node, "clock-output-names", &clk_name))  in sun7i_a20_gmac_clk_setup()
82 	gate->reg = reg;  in sun7i_a20_gmac_clk_setup()
83 	gate->bit_idx = SUN7I_A20_GMAC_GPIT;  in sun7i_a20_gmac_clk_setup()
84 	gate->lock = &gmac_lock;  in sun7i_a20_gmac_clk_setup()
85 	mux->reg = reg;  in sun7i_a20_gmac_clk_setup()
86 	mux->mask = SUN7I_A20_GMAC_MASK;  in sun7i_a20_gmac_clk_setup()
87 	mux->table = sun7i_a20_gmac_mux_table;  in sun7i_a20_gmac_clk_setup()
88 	mux->lock = &gmac_lock;  in sun7i_a20_gmac_clk_setup()
92 			&mux->hw, &clk_mux_ops,  in sun7i_a20_gmac_clk_setup()
94 			&gate->hw, &clk_gate_ops,  in sun7i_a20_gmac_clk_setup()
111 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",