Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
39 .enable = BIT(31),
40 .lock = BIT(28),
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
53 .enable = BIT(31),
54 .lock = BIT(28),
60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
68 .enable = BIT(31),
69 .lock = BIT(28),
75 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
83 .enable = BIT(31),
84 .lock = BIT(28),
92 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
100 .enable = BIT(31),
101 .lock = BIT(28),
109 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
117 .enable = BIT(31),
118 .lock = BIT(28),
124 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
136 .enable = BIT(31),
137 .lock = BIT(28),
146 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
154 .enable = BIT(31),
155 .lock = BIT(28),
164 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
172 .enable = BIT(31),
173 .lock = BIT(28),
182 .hw.init = CLK_HW_INIT("pll-video2", "osc24M",
190 .enable = BIT(31),
191 .lock = BIT(28),
197 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
205 .enable = BIT(31),
206 .lock = BIT(28),
212 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
227 .enable = BIT(31),
228 .lock = BIT(28),
233 .hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M",
240 "iosc", "pll-cpux", "pll-periph0" };
242 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
244 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
247 "iosc", "pll-periph0" };
248 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
253 24, 2, /* mux */
257 "psi-ahb1-ahb2",
258 "pll-periph0" };
262 24, 2, /* mux */
268 24, 2, /* mux */
274 24, 2, /* mux */
277 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
278 "pll-ddr0", "pll-ddr1" };
281 24, 2, /* mux */
282 BIT(31), /* gate */
285 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
288 24, 1, /* mux */
289 BIT(31), /* gate */
292 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
293 0x60c, BIT(0), 0);
299 24, 1, /* mux */
300 BIT(31), /* gate */
303 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
304 0x62c, BIT(0), 0);
308 24, 1, /* mux */
309 BIT(31), /* gate */
312 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
313 0x63c, BIT(0), 0);
315 static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" };
318 24, 1, /* mux */
319 BIT(31), /* gate */
321 static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674,
323 BIT(31),/* gate */
326 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
327 0x67c, BIT(0), 0);
329 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
333 24, 1, /* mux */
334 BIT(31),/* gate */
337 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
338 0x68c, BIT(0), 0);
340 static const char * const ve_parents[] = { "pll-ve" };
343 24, 1, /* mux */
344 BIT(31), /* gate */
347 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
348 0x69c, BIT(0), 0);
350 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
351 0x70c, BIT(0), 0);
353 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
354 0x73c, BIT(0), 0);
356 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
358 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
359 0x78c, BIT(0), 0);
361 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
362 0x79c, BIT(0), 0);
364 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
366 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
368 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
371 .mux = _SUNXI_CCU_MUX(24, 2),
381 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
382 0x804, BIT(0), 0);
383 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
384 0x804, BIT(1), 0);
385 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
386 0x804, BIT(2), 0);
387 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
388 0x804, BIT(3), 0);
389 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
390 0x804, BIT(5), 0);
391 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
392 0x804, BIT(10), 0);
394 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
395 0x80c, BIT(0), CLK_IS_CRITICAL);
397 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
398 "pll-periph1", "pll-periph0-2x",
399 "pll-periph1-2x" };
403 24, 3, /* mux */
404 BIT(31),/* gate */
410 24, 3, /* mux */
411 BIT(31),/* gate */
414 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
416 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
417 "pll-periph1-2x" };
421 24, 2, /* mux */
422 BIT(31), /* gate */
423 2, /* post-div */
429 24, 2, /* mux */
430 BIT(31), /* gate */
431 2, /* post-div */
437 24, 2, /* mux */
438 BIT(31), /* gate */
439 2, /* post-div */
442 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
443 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
444 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
446 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
447 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
448 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
449 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
450 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
451 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
453 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
454 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
455 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
456 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
457 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0);
462 24, 3, /* mux */
463 BIT(31),/* gate */
469 24, 3, /* mux */
470 BIT(31),/* gate */
473 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
474 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
476 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970,
477 BIT(31) | BIT(30), 0);
479 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
480 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
482 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
486 24, 1, /* mux */
487 BIT(31),/* gate */
490 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
492 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
494 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
495 "pll-audio-4x", "pll-audio-hs" };
497 .enable = BIT(31),
499 .mux = _SUNXI_CCU_MUX(24, 2),
509 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
512 .enable = BIT(31),
514 .mux = _SUNXI_CCU_MUX(24, 2),
524 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
526 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x",
529 24, 2, /* mux */
530 BIT(31), /* gate */
532 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
535 24, 2, /* mux */
536 BIT(31), /* gate */
539 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c,
540 BIT(0), 0);
543 .enable = BIT(31),
545 .mux = _SUNXI_CCU_MUX(24, 2),
548 .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
555 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
566 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
567 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
569 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
570 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
572 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0);
573 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0);
575 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
576 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0);
578 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
579 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
580 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0);
581 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
582 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
583 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
584 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0);
585 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
586 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
588 static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0);
590 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x",
591 "pll-video2", "pll-video2-4x" };
594 24, 2, /* mux */
595 BIT(31), /* gate */
598 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
600 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
607 .enable = BIT(31) | BIT(30),
610 .shift = 24,
620 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
627 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
629 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
630 0xb5c, BIT(0), 0);
632 static const char * const tcon_tv_parents[] = { "pll-video0",
633 "pll-video0-4x",
634 "pll-video1",
635 "pll-video1-4x" };
636 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
640 24, 3, /* mux */
641 BIT(31), /* gate */
643 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1",
647 24, 3, /* mux */
648 BIT(31), /* gate */
651 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
652 0xb9c, BIT(0), 0);
653 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3",
654 0xb9c, BIT(1), 0);
660 24, 3, /* mux */
661 BIT(31), /* gate */
664 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
665 0xbbc, BIT(0), 0);
666 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3",
667 0xbbc, BIT(1), 0);
669 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
672 24, 2, /* mux */
673 BIT(31), /* gate */
676 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
686 * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
687 * rates can be set exactly in conjunction with sigma-delta modulation.
689 static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
692 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
695 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
697 24, 1, CLK_SET_RATE_PARENT);
703 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
711 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
715 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
718 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
721 static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x",
982 [RST_MBUS] = { 0x540, BIT(30) },
984 [RST_BUS_DE] = { 0x60c, BIT(16) },
985 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
986 [RST_BUS_GPU] = { 0x67c, BIT(16) },
987 [RST_BUS_CE] = { 0x68c, BIT(16) },
988 [RST_BUS_VE] = { 0x69c, BIT(16) },
989 [RST_BUS_DMA] = { 0x70c, BIT(16) },
990 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
991 [RST_BUS_DBG] = { 0x78c, BIT(16) },
992 [RST_BUS_PSI] = { 0x79c, BIT(16) },
993 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
994 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
995 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
996 [RST_BUS_NAND] = { 0x82c, BIT(16) },
997 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
998 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
999 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1000 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1001 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1002 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1003 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1004 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1005 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1006 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1007 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1008 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1009 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1010 [RST_BUS_I2C4] = { 0x91c, BIT(20) },
1011 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1012 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1013 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1014 [RST_BUS_EMAC1] = { 0x97c, BIT(17) },
1015 [RST_BUS_TS] = { 0x9bc, BIT(16) },
1016 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1017 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1018 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1019 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
1020 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
1022 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1023 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1024 [RST_USB_PHY2] = { 0xa78, BIT(30) },
1025 [RST_USB_PHY3] = { 0xa7c, BIT(30) },
1026 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1027 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1028 [RST_BUS_OHCI2] = { 0xa8c, BIT(18) },
1029 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
1030 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1031 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1032 [RST_BUS_EHCI2] = { 0xa8c, BIT(22) },
1033 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
1034 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1035 [RST_BUS_KEYADC] = { 0xa9c, BIT(16) },
1037 [RST_BUS_HDMI] = { 0xb1c, BIT(16) },
1038 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1039 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
1040 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1041 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1042 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1043 [RST_BUS_TVE0] = { 0xbbc, BIT(17) },
1044 [RST_BUS_HDCP] = { 0xc4c, BIT(16) },
1100 val |= BIT(29) | BIT(27); in sun50i_h616_ccu_setup()
1107 * See the comment before pll-video0 definition for the reason. in sun50i_h616_ccu_setup()
1111 val &= ~BIT(0); in sun50i_h616_ccu_setup()
1123 val &= ~GENMASK(25, 24); in sun50i_h616_ccu_setup()
1128 * Force the post-divider of pll-audio to 12 and the output divider in sun50i_h616_ccu_setup()
1132 val &= ~(GENMASK(21, 16) | BIT(0)); in sun50i_h616_ccu_setup()
1133 writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG); in sun50i_h616_ccu_setup()
1141 val |= BIT(24); in sun50i_h616_ccu_setup()
1149 CLK_OF_DECLARE(sun50i_h616_ccu, "allwinner,sun50i-h616-ccu",