Lines Matching +full:1 +full:mhz
25 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
47 #define SPEAR1310_GPT_APB_VAL 1
48 #define SPEAR1310_GPT_CLK_MASK 1
54 #define SPEAR1310_UART_CLK_OSC24_VAL 1
60 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
63 #define SPEAR1310_C3_CLK_MASK 1
64 #define SPEAR1310_C3_CLK_SHIFT 1
69 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
87 #define SPEAR1310_I2S_REF_SEL_MASK 1
136 #define SPEAR1310_SYSROM_CLK_ENB 1
148 #define SPEAR1310_DDR_CORE_CLK_ENB 1
169 #define SPEAR1310_PCLK_CLK_ENB 1
176 #define SPEAR1310_TDM_CLK_MASK 1
179 #define SPEAR1310_I2C_CLK_MASK 1
187 #define SPEAR1310_GPT64_CLK_MASK 1
189 #define SPEAR1310_RAS_UART_CLK_MASK 1
195 #define SPEAR1310_PCI_CLK_MASK 1
228 #define SPEAR1310_MII0_CLK_ENB 1
235 /* PCLK 24MHz */
236 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
237 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
238 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
239 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
240 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
241 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
242 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
247 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
248 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
249 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
250 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
255 /* For VCO1div2 = 500 MHz */
256 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
257 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
258 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
259 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
260 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
261 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
269 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
270 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
275 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
276 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
278 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
279 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
280 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
282 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
284 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
314 /* For parent clk = 49.152 MHz */
315 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
316 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
317 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
318 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
321 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
322 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
324 {.xscale = 1, .yscale = 3, .eq = 0},
326 /* For parent clk = 49.152 MHz */
327 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
329 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
334 /* For i2s_ref_clk = 12.288MHz */
335 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
336 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
340 /* possible adc range is 2.5 MHz to 20 MHz. */
342 /* For ahb = 166.67 MHz */
343 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
344 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
345 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
346 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
351 /* For vco1div4 = 250 MHz */
352 {.div = 0x14000}, /* 25 MHz */
353 {.div = 0x0A000}, /* 50 MHz */
354 {.div = 0x05000}, /* 100 MHz */
355 {.div = 0x02000}, /* 250 MHz */
412 /* clock derived from 24 or 25 MHz osc clk */ in spear1310_clk_init()
462 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, in spear1310_clk_init()
466 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, in spear1310_clk_init()
470 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, in spear1310_clk_init()
474 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, in spear1310_clk_init()
479 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, in spear1310_clk_init()
487 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, in spear1310_clk_init()
488 1); in spear1310_clk_init()
493 CLK_SET_RATE_PARENT, 1, 2); in spear1310_clk_init()
496 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, in spear1310_clk_init()
500 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, in spear1310_clk_init()
504 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, in spear1310_clk_init()
508 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, in spear1310_clk_init()
910 clk_register_clkdev(clk, NULL, "c_can_platform.1"); in spear1310_clk_init()
938 clk_register_clkdev(clk, "stmmacphy.1", NULL); in spear1310_clk_init()
1122 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); in spear1310_clk_init()