26  * @pd: PRCI context
30  * address of the PRCI register target described by @pd, and return
35  * Return: the contents of the register described by @pd and @offs.
37 static u32 __prci_readl(struct __prci_data *pd, u32 offs)  in __prci_readl()  argument
39 	return readl_relaxed(pd->va + offs);  in __prci_readl()
42 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)  in __prci_writel()  argument
44 	writel_relaxed(v, pd->va + offs);  in __prci_writel()
122  * @pd: PRCI context
126  * the PRCI identified by @pd, and store it into the local configuration
130  *          @pd and @pwd from changing during execution.
132 static void __prci_wrpll_read_cfg0(struct __prci_data *pd,  in __prci_wrpll_read_cfg0()  argument
135 	__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));  in __prci_wrpll_read_cfg0()
140  * @pd: PRCI context
150  *          @pd and @pwd from changing during execution.
152 static void __prci_wrpll_write_cfg0(struct __prci_data *pd,  in __prci_wrpll_write_cfg0()  argument
156 	__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);  in __prci_wrpll_write_cfg0()
164  * @pd: PRCI context
168 static void __prci_wrpll_write_cfg1(struct __prci_data *pd,  in __prci_wrpll_write_cfg1()  argument
172 	__prci_writel(enable, pwd->cfg1_offs, pd);  in __prci_wrpll_write_cfg1()
211 	struct __prci_data *pd = pc->pd;  in sifive_prci_wrpll_set_rate()  local
219 		pwd->enable_bypass(pd);  in sifive_prci_wrpll_set_rate()
221 	__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);  in sifive_prci_wrpll_set_rate()
232 	struct __prci_data *pd = pc->pd;  in sifive_clk_is_enabled()  local
235 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_clk_is_enabled()
247 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_enable()  local
252 	__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);  in sifive_prci_clock_enable()
255 		pwd->disable_bypass(pd);  in sifive_prci_clock_enable()
264 	struct __prci_data *pd = pc->pd;  in sifive_prci_clock_disable()  local
268 		pwd->enable_bypass(pd);  in sifive_prci_clock_disable()
270 	r = __prci_readl(pd, pwd->cfg1_offs);  in sifive_prci_clock_disable()
273 	__prci_wrpll_write_cfg1(pd, pwd, r);  in sifive_prci_clock_disable()
282 	struct __prci_data *pd = pc->pd;  in sifive_prci_tlclksel_recalc_rate()  local
286 	v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);  in sifive_prci_tlclksel_recalc_rate()
299 	struct __prci_data *pd = pc->pd;  in sifive_prci_hfpclkplldiv_recalc_rate()  local
300 	u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);  in sifive_prci_hfpclkplldiv_recalc_rate()
311  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
318 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)  in sifive_prci_coreclksel_use_hfclk()  argument
322 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_hfclk()
324 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_hfclk()
326 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_hfclk()
332  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
339 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)  in sifive_prci_coreclksel_use_corepll()  argument
343 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_corepll()
345 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_corepll()
347 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_corepll()
353  * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
361 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)  in sifive_prci_coreclksel_use_final_corepll()  argument
365 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);  in sifive_prci_coreclksel_use_final_corepll()
367 	__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);  in sifive_prci_coreclksel_use_final_corepll()
369 	r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);	/* barrier */  in sifive_prci_coreclksel_use_final_corepll()
375  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
382 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)  in sifive_prci_corepllsel_use_dvfscorepll()  argument
386 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_dvfscorepll()
388 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_dvfscorepll()
390 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_dvfscorepll()
396  * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
403 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)  in sifive_prci_corepllsel_use_corepll()  argument
407 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);  in sifive_prci_corepllsel_use_corepll()
409 	__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);  in sifive_prci_corepllsel_use_corepll()
411 	r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);	/* barrier */  in sifive_prci_corepllsel_use_corepll()
417  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
424 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)  in sifive_prci_hfpclkpllsel_use_hfclk()  argument
428 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfclk()
430 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfclk()
432 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfclk()
438  * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
445 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)  in sifive_prci_hfpclkpllsel_use_hfpclkpll()  argument
449 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
451 	__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
453 	r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);	/* barrier */  in sifive_prci_hfpclkpllsel_use_hfpclkpll()
460 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_is_enabled()  local
463 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);  in sifive_prci_pcie_aux_clock_is_enabled()
474 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_enable()  local
480 	__prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);  in sifive_prci_pcie_aux_clock_enable()
481 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_enable()
489 	struct __prci_data *pd = pc->pd;  in sifive_prci_pcie_aux_clock_disable()  local
492 	__prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);  in sifive_prci_pcie_aux_clock_disable()
493 	r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);	/* barrier */  in sifive_prci_pcie_aux_clock_disable()
500  * @pd: The pointer for PRCI per-device instance data
508 static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,  in __prci_register_clocks()  argument
532 		pic->pd = pd;  in __prci_register_clocks()
535 			__prci_wrpll_read_cfg0(pd, pic->pwd);  in __prci_register_clocks()
551 		pd->hw_clks.hws[i] = &pic->hw;  in __prci_register_clocks()
554 	pd->hw_clks.num = i;  in __prci_register_clocks()
557 					&pd->hw_clks);  in __prci_register_clocks()
576 	struct __prci_data *pd;  in sifive_prci_probe()  local
582 	pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);  in sifive_prci_probe()
583 	if (!pd)  in sifive_prci_probe()
587 	pd->va = devm_ioremap_resource(dev, res);  in sifive_prci_probe()
588 	if (IS_ERR(pd->va))  in sifive_prci_probe()
589 		return PTR_ERR(pd->va);  in sifive_prci_probe()
591 	pd->reset.rcdev.owner = THIS_MODULE;  in sifive_prci_probe()
592 	pd->reset.rcdev.nr_resets = PRCI_RST_NR;  in sifive_prci_probe()
593 	pd->reset.rcdev.ops = &reset_simple_ops;  in sifive_prci_probe()
594 	pd->reset.rcdev.of_node = pdev->dev.of_node;  in sifive_prci_probe()
595 	pd->reset.active_low = true;  in sifive_prci_probe()
596 	pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;  in sifive_prci_probe()
597 	spin_lock_init(&pd->reset.lock);  in sifive_prci_probe()
599 	r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);  in sifive_prci_probe()
604 	r = __prci_register_clocks(dev, pd, desc);  in sifive_prci_probe()